//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// The confidential and proprietary information contained in this file may     
// only be used by a person authorised under and to the extent permitted       
// by a subsisting licensing agreement from ARM Limited.                       
//                                                                             
//            (C) COPYRIGHT 2005-2013 ARM Limited.
//                ALL RIGHTS RESERVED                                          
//                                                                             
// This entire notice must be reproduced on all copies of this file            
// and copies of this file may only be made by a person if such person is      
// permitted to do so under the terms of a subsisting license agreement        
// from ARM Limited.                                                           
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Top-Level Verilog file is auto-generated by AMBA Designer ADr3p4-00rel0-build-0086
//                                                                             
// Stitcher: generic_stitcher_core v3.1, built on Sep 18 2013
//                                                                             
// Filename: nic400_ysyx_rv32.v
// Created : Mon May 27 20:11:40 2024                            
//                                                                             
//- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Generated with Validator version0.1


//-----------------------------------------------------------------------------
// Module Declaration nic400_ysyx_rv32
//-----------------------------------------------------------------------------

module nic400_ysyx_rv32 (
  
// Instance: u_cd_clk_aud_12288k, Port: i2s_slv_apb4

  paddr_i2s_slv_apb4,
  pselx_i2s_slv_apb4,
  penable_i2s_slv_apb4,
  pwrite_i2s_slv_apb4,
  prdata_i2s_slv_apb4,
  pwdata_i2s_slv_apb4,
  pprot_i2s_slv_apb4,
  pstrb_i2s_slv_apb4,
  pready_i2s_slv_apb4,
  pslverr_i2s_slv_apb4,
  
// Instance: u_cd_clk_core_200_800m, Port: cpu_mst_axi4

  awid_cpu_mst_axi4,
  awaddr_cpu_mst_axi4,
  awlen_cpu_mst_axi4,
  awsize_cpu_mst_axi4,
  awburst_cpu_mst_axi4,
  awlock_cpu_mst_axi4,
  awcache_cpu_mst_axi4,
  awprot_cpu_mst_axi4,
  awvalid_cpu_mst_axi4,
  awready_cpu_mst_axi4,
  wdata_cpu_mst_axi4,
  wstrb_cpu_mst_axi4,
  wlast_cpu_mst_axi4,
  wvalid_cpu_mst_axi4,
  wready_cpu_mst_axi4,
  bid_cpu_mst_axi4,
  bresp_cpu_mst_axi4,
  bvalid_cpu_mst_axi4,
  bready_cpu_mst_axi4,
  arid_cpu_mst_axi4,
  araddr_cpu_mst_axi4,
  arlen_cpu_mst_axi4,
  arsize_cpu_mst_axi4,
  arburst_cpu_mst_axi4,
  arlock_cpu_mst_axi4,
  arcache_cpu_mst_axi4,
  arprot_cpu_mst_axi4,
  arvalid_cpu_mst_axi4,
  arready_cpu_mst_axi4,
  rid_cpu_mst_axi4,
  rdata_cpu_mst_axi4,
  rresp_cpu_mst_axi4,
  rlast_cpu_mst_axi4,
  rvalid_cpu_mst_axi4,
  rready_cpu_mst_axi4,
  
// Instance: u_cd_clk_core_200_800m, Port: dma_axi4_cpu_m

  awid_dma_axi4_cpu_m,
  awaddr_dma_axi4_cpu_m,
  awlen_dma_axi4_cpu_m,
  awsize_dma_axi4_cpu_m,
  awburst_dma_axi4_cpu_m,
  awlock_dma_axi4_cpu_m,
  awcache_dma_axi4_cpu_m,
  awprot_dma_axi4_cpu_m,
  awvalid_dma_axi4_cpu_m,
  awready_dma_axi4_cpu_m,
  wdata_dma_axi4_cpu_m,
  wstrb_dma_axi4_cpu_m,
  wlast_dma_axi4_cpu_m,
  wvalid_dma_axi4_cpu_m,
  wready_dma_axi4_cpu_m,
  bid_dma_axi4_cpu_m,
  bresp_dma_axi4_cpu_m,
  bvalid_dma_axi4_cpu_m,
  bready_dma_axi4_cpu_m,
  arid_dma_axi4_cpu_m,
  araddr_dma_axi4_cpu_m,
  arlen_dma_axi4_cpu_m,
  arsize_dma_axi4_cpu_m,
  arburst_dma_axi4_cpu_m,
  arlock_dma_axi4_cpu_m,
  arcache_dma_axi4_cpu_m,
  arprot_dma_axi4_cpu_m,
  arvalid_dma_axi4_cpu_m,
  arready_dma_axi4_cpu_m,
  rid_dma_axi4_cpu_m,
  rdata_dma_axi4_cpu_m,
  rresp_dma_axi4_cpu_m,
  rlast_dma_axi4_cpu_m,
  rvalid_dma_axi4_cpu_m,
  rready_dma_axi4_cpu_m,
  
// Instance: u_cd_clk_core_200_800m, Port: sram_slv_axi4

  awid_sram_slv_axi4,
  awaddr_sram_slv_axi4,
  awlen_sram_slv_axi4,
  awsize_sram_slv_axi4,
  awburst_sram_slv_axi4,
  awlock_sram_slv_axi4,
  awcache_sram_slv_axi4,
  awprot_sram_slv_axi4,
  awvalid_sram_slv_axi4,
  awready_sram_slv_axi4,
  wdata_sram_slv_axi4,
  wstrb_sram_slv_axi4,
  wlast_sram_slv_axi4,
  wvalid_sram_slv_axi4,
  wready_sram_slv_axi4,
  bid_sram_slv_axi4,
  bresp_sram_slv_axi4,
  bvalid_sram_slv_axi4,
  bready_sram_slv_axi4,
  arid_sram_slv_axi4,
  araddr_sram_slv_axi4,
  arlen_sram_slv_axi4,
  arsize_sram_slv_axi4,
  arburst_sram_slv_axi4,
  arlock_sram_slv_axi4,
  arcache_sram_slv_axi4,
  arprot_sram_slv_axi4,
  arvalid_sram_slv_axi4,
  arready_sram_slv_axi4,
  rid_sram_slv_axi4,
  rdata_sram_slv_axi4,
  rresp_sram_slv_axi4,
  rlast_sram_slv_axi4,
  rvalid_sram_slv_axi4,
  rready_sram_slv_axi4,
  
// Instance: u_cd_clk_peri_100m, Port: archinfo_slv_apb4

  paddr_archinfo_slv_apb4,
  pselx_archinfo_slv_apb4,
  penable_archinfo_slv_apb4,
  pwrite_archinfo_slv_apb4,
  prdata_archinfo_slv_apb4,
  pwdata_archinfo_slv_apb4,
  pprot_archinfo_slv_apb4,
  pstrb_archinfo_slv_apb4,
  pready_archinfo_slv_apb4,
  pslverr_archinfo_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: clint_slv_apb4

  paddr_clint_slv_apb4,
  pselx_clint_slv_apb4,
  penable_clint_slv_apb4,
  pwrite_clint_slv_apb4,
  prdata_clint_slv_apb4,
  pwdata_clint_slv_apb4,
  pprot_clint_slv_apb4,
  pstrb_clint_slv_apb4,
  pready_clint_slv_apb4,
  pslverr_clint_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: crc_slv_apb4

  paddr_crc_slv_apb4,
  pselx_crc_slv_apb4,
  penable_crc_slv_apb4,
  pwrite_crc_slv_apb4,
  prdata_crc_slv_apb4,
  pwdata_crc_slv_apb4,
  pprot_crc_slv_apb4,
  pstrb_crc_slv_apb4,
  pready_crc_slv_apb4,
  pslverr_crc_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: gpio_slv_apb4

  paddr_gpio_slv_apb4,
  pselx_gpio_slv_apb4,
  penable_gpio_slv_apb4,
  pwrite_gpio_slv_apb4,
  prdata_gpio_slv_apb4,
  pwdata_gpio_slv_apb4,
  pprot_gpio_slv_apb4,
  pstrb_gpio_slv_apb4,
  pready_gpio_slv_apb4,
  pslverr_gpio_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: i2c_slv_apb4

  paddr_i2c_slv_apb4,
  pselx_i2c_slv_apb4,
  penable_i2c_slv_apb4,
  pwrite_i2c_slv_apb4,
  prdata_i2c_slv_apb4,
  pwdata_i2c_slv_apb4,
  pprot_i2c_slv_apb4,
  pstrb_i2c_slv_apb4,
  pready_i2c_slv_apb4,
  pslverr_i2c_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: plic_slv_apb4

  paddr_plic_slv_apb4,
  pselx_plic_slv_apb4,
  penable_plic_slv_apb4,
  pwrite_plic_slv_apb4,
  prdata_plic_slv_apb4,
  pwdata_plic_slv_apb4,
  pprot_plic_slv_apb4,
  pstrb_plic_slv_apb4,
  pready_plic_slv_apb4,
  pslverr_plic_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: ps2_slv_apb4

  paddr_ps2_slv_apb4,
  pselx_ps2_slv_apb4,
  penable_ps2_slv_apb4,
  pwrite_ps2_slv_apb4,
  prdata_ps2_slv_apb4,
  pwdata_ps2_slv_apb4,
  pprot_ps2_slv_apb4,
  pstrb_ps2_slv_apb4,
  pready_ps2_slv_apb4,
  pslverr_ps2_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: psram_slv_apb4

  paddr_psram_slv_apb4,
  pselx_psram_slv_apb4,
  penable_psram_slv_apb4,
  pwrite_psram_slv_apb4,
  prdata_psram_slv_apb4,
  pwdata_psram_slv_apb4,
  pprot_psram_slv_apb4,
  pstrb_psram_slv_apb4,
  pready_psram_slv_apb4,
  pslverr_psram_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: psram_slv_axi4

  awid_psram_slv_axi4,
  awaddr_psram_slv_axi4,
  awlen_psram_slv_axi4,
  awsize_psram_slv_axi4,
  awburst_psram_slv_axi4,
  awlock_psram_slv_axi4,
  awcache_psram_slv_axi4,
  awprot_psram_slv_axi4,
  awvalid_psram_slv_axi4,
  awready_psram_slv_axi4,
  wdata_psram_slv_axi4,
  wstrb_psram_slv_axi4,
  wlast_psram_slv_axi4,
  wvalid_psram_slv_axi4,
  wready_psram_slv_axi4,
  bid_psram_slv_axi4,
  bresp_psram_slv_axi4,
  bvalid_psram_slv_axi4,
  bready_psram_slv_axi4,
  arid_psram_slv_axi4,
  araddr_psram_slv_axi4,
  arlen_psram_slv_axi4,
  arsize_psram_slv_axi4,
  arburst_psram_slv_axi4,
  arlock_psram_slv_axi4,
  arcache_psram_slv_axi4,
  arprot_psram_slv_axi4,
  arvalid_psram_slv_axi4,
  arready_psram_slv_axi4,
  rid_psram_slv_axi4,
  rdata_psram_slv_axi4,
  rresp_psram_slv_axi4,
  rlast_psram_slv_axi4,
  rvalid_psram_slv_axi4,
  rready_psram_slv_axi4,
  
// Instance: u_cd_clk_peri_100m, Port: pwm0_slv_apb4

  paddr_pwm0_slv_apb4,
  pselx_pwm0_slv_apb4,
  penable_pwm0_slv_apb4,
  pwrite_pwm0_slv_apb4,
  prdata_pwm0_slv_apb4,
  pwdata_pwm0_slv_apb4,
  pprot_pwm0_slv_apb4,
  pstrb_pwm0_slv_apb4,
  pready_pwm0_slv_apb4,
  pslverr_pwm0_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: pwm1_slv_apb4

  paddr_pwm1_slv_apb4,
  pselx_pwm1_slv_apb4,
  penable_pwm1_slv_apb4,
  pwrite_pwm1_slv_apb4,
  prdata_pwm1_slv_apb4,
  pwdata_pwm1_slv_apb4,
  pprot_pwm1_slv_apb4,
  pstrb_pwm1_slv_apb4,
  pready_pwm1_slv_apb4,
  pslverr_pwm1_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: pwm2_slv_apb4

  paddr_pwm2_slv_apb4,
  pselx_pwm2_slv_apb4,
  penable_pwm2_slv_apb4,
  pwrite_pwm2_slv_apb4,
  prdata_pwm2_slv_apb4,
  pwdata_pwm2_slv_apb4,
  pprot_pwm2_slv_apb4,
  pstrb_pwm2_slv_apb4,
  pready_pwm2_slv_apb4,
  pslverr_pwm2_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: qspi_slv_apb4

  paddr_qspi_slv_apb4,
  pselx_qspi_slv_apb4,
  penable_qspi_slv_apb4,
  pwrite_qspi_slv_apb4,
  prdata_qspi_slv_apb4,
  pwdata_qspi_slv_apb4,
  pprot_qspi_slv_apb4,
  pstrb_qspi_slv_apb4,
  pready_qspi_slv_apb4,
  pslverr_qspi_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: rcu_slv_apb4

  paddr_rcu_slv_apb4,
  pselx_rcu_slv_apb4,
  penable_rcu_slv_apb4,
  pwrite_rcu_slv_apb4,
  prdata_rcu_slv_apb4,
  pwdata_rcu_slv_apb4,
  pprot_rcu_slv_apb4,
  pstrb_rcu_slv_apb4,
  pready_rcu_slv_apb4,
  pslverr_rcu_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: rng_slv_apb4

  paddr_rng_slv_apb4,
  pselx_rng_slv_apb4,
  penable_rng_slv_apb4,
  pwrite_rng_slv_apb4,
  prdata_rng_slv_apb4,
  pwdata_rng_slv_apb4,
  pprot_rng_slv_apb4,
  pstrb_rng_slv_apb4,
  pready_rng_slv_apb4,
  pslverr_rng_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: rtc_slv_apb4

  paddr_rtc_slv_apb4,
  pselx_rtc_slv_apb4,
  penable_rtc_slv_apb4,
  pwrite_rtc_slv_apb4,
  prdata_rtc_slv_apb4,
  pwdata_rtc_slv_apb4,
  pprot_rtc_slv_apb4,
  pstrb_rtc_slv_apb4,
  pready_rtc_slv_apb4,
  pslverr_rtc_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: sdram_slv_axi4

  awid_sdram_slv_axi4,
  awaddr_sdram_slv_axi4,
  awlen_sdram_slv_axi4,
  awsize_sdram_slv_axi4,
  awburst_sdram_slv_axi4,
  awlock_sdram_slv_axi4,
  awcache_sdram_slv_axi4,
  awprot_sdram_slv_axi4,
  awvalid_sdram_slv_axi4,
  awready_sdram_slv_axi4,
  wdata_sdram_slv_axi4,
  wstrb_sdram_slv_axi4,
  wlast_sdram_slv_axi4,
  wvalid_sdram_slv_axi4,
  wready_sdram_slv_axi4,
  bid_sdram_slv_axi4,
  bresp_sdram_slv_axi4,
  bvalid_sdram_slv_axi4,
  bready_sdram_slv_axi4,
  arid_sdram_slv_axi4,
  araddr_sdram_slv_axi4,
  arlen_sdram_slv_axi4,
  arsize_sdram_slv_axi4,
  arburst_sdram_slv_axi4,
  arlock_sdram_slv_axi4,
  arcache_sdram_slv_axi4,
  arprot_sdram_slv_axi4,
  arvalid_sdram_slv_axi4,
  arready_sdram_slv_axi4,
  rid_sdram_slv_axi4,
  rdata_sdram_slv_axi4,
  rresp_sdram_slv_axi4,
  rlast_sdram_slv_axi4,
  rvalid_sdram_slv_axi4,
  rready_sdram_slv_axi4,
  
// Instance: u_cd_clk_peri_100m, Port: spi0_slv_apb4

  paddr_spi0_slv_apb4,
  pselx_spi0_slv_apb4,
  penable_spi0_slv_apb4,
  pwrite_spi0_slv_apb4,
  prdata_spi0_slv_apb4,
  pwdata_spi0_slv_apb4,
  pprot_spi0_slv_apb4,
  pstrb_spi0_slv_apb4,
  pready_spi0_slv_apb4,
  pslverr_spi0_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: spi1_slv_apb4

  paddr_spi1_slv_apb4,
  pselx_spi1_slv_apb4,
  penable_spi1_slv_apb4,
  pwrite_spi1_slv_apb4,
  prdata_spi1_slv_apb4,
  pwdata_spi1_slv_apb4,
  pprot_spi1_slv_apb4,
  pstrb_spi1_slv_apb4,
  pready_spi1_slv_apb4,
  pslverr_spi1_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: tim0_slv_apb4

  paddr_tim0_slv_apb4,
  pselx_tim0_slv_apb4,
  penable_tim0_slv_apb4,
  pwrite_tim0_slv_apb4,
  prdata_tim0_slv_apb4,
  pwdata_tim0_slv_apb4,
  pprot_tim0_slv_apb4,
  pstrb_tim0_slv_apb4,
  pready_tim0_slv_apb4,
  pslverr_tim0_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: tim1_slv_apb4

  paddr_tim1_slv_apb4,
  pselx_tim1_slv_apb4,
  penable_tim1_slv_apb4,
  pwrite_tim1_slv_apb4,
  prdata_tim1_slv_apb4,
  pwdata_tim1_slv_apb4,
  pprot_tim1_slv_apb4,
  pstrb_tim1_slv_apb4,
  pready_tim1_slv_apb4,
  pslverr_tim1_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: tim2_slv_apb4

  paddr_tim2_slv_apb4,
  pselx_tim2_slv_apb4,
  penable_tim2_slv_apb4,
  pwrite_tim2_slv_apb4,
  prdata_tim2_slv_apb4,
  pwdata_tim2_slv_apb4,
  pprot_tim2_slv_apb4,
  pstrb_tim2_slv_apb4,
  pready_tim2_slv_apb4,
  pslverr_tim2_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: tim3_slv_apb4

  paddr_tim3_slv_apb4,
  pselx_tim3_slv_apb4,
  penable_tim3_slv_apb4,
  pwrite_tim3_slv_apb4,
  prdata_tim3_slv_apb4,
  pwdata_tim3_slv_apb4,
  pprot_tim3_slv_apb4,
  pstrb_tim3_slv_apb4,
  pready_tim3_slv_apb4,
  pslverr_tim3_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: uart_slv_apb4

  paddr_uart_slv_apb4,
  pselx_uart_slv_apb4,
  penable_uart_slv_apb4,
  pwrite_uart_slv_apb4,
  prdata_uart_slv_apb4,
  pwdata_uart_slv_apb4,
  pprot_uart_slv_apb4,
  pstrb_uart_slv_apb4,
  pready_uart_slv_apb4,
  pslverr_uart_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: vgalcd_mst_axi4

  awid_vgalcd_mst_axi4,
  awaddr_vgalcd_mst_axi4,
  awlen_vgalcd_mst_axi4,
  awsize_vgalcd_mst_axi4,
  awburst_vgalcd_mst_axi4,
  awlock_vgalcd_mst_axi4,
  awcache_vgalcd_mst_axi4,
  awprot_vgalcd_mst_axi4,
  awvalid_vgalcd_mst_axi4,
  awready_vgalcd_mst_axi4,
  wdata_vgalcd_mst_axi4,
  wstrb_vgalcd_mst_axi4,
  wlast_vgalcd_mst_axi4,
  wvalid_vgalcd_mst_axi4,
  wready_vgalcd_mst_axi4,
  bid_vgalcd_mst_axi4,
  bresp_vgalcd_mst_axi4,
  bvalid_vgalcd_mst_axi4,
  bready_vgalcd_mst_axi4,
  arid_vgalcd_mst_axi4,
  araddr_vgalcd_mst_axi4,
  arlen_vgalcd_mst_axi4,
  arsize_vgalcd_mst_axi4,
  arburst_vgalcd_mst_axi4,
  arlock_vgalcd_mst_axi4,
  arcache_vgalcd_mst_axi4,
  arprot_vgalcd_mst_axi4,
  arvalid_vgalcd_mst_axi4,
  arready_vgalcd_mst_axi4,
  rid_vgalcd_mst_axi4,
  rdata_vgalcd_mst_axi4,
  rresp_vgalcd_mst_axi4,
  rlast_vgalcd_mst_axi4,
  rvalid_vgalcd_mst_axi4,
  rready_vgalcd_mst_axi4,
  
// Instance: u_cd_clk_peri_100m, Port: vgalcd_slv_apb4

  paddr_vgalcd_slv_apb4,
  pselx_vgalcd_slv_apb4,
  penable_vgalcd_slv_apb4,
  pwrite_vgalcd_slv_apb4,
  prdata_vgalcd_slv_apb4,
  pwdata_vgalcd_slv_apb4,
  pprot_vgalcd_slv_apb4,
  pstrb_vgalcd_slv_apb4,
  pready_vgalcd_slv_apb4,
  pslverr_vgalcd_slv_apb4,
  
// Instance: u_cd_clk_peri_100m, Port: wdg_slv_apb4

  paddr_wdg_slv_apb4,
  pselx_wdg_slv_apb4,
  penable_wdg_slv_apb4,
  pwrite_wdg_slv_apb4,
  prdata_wdg_slv_apb4,
  pwdata_wdg_slv_apb4,
  pprot_wdg_slv_apb4,
  pstrb_wdg_slv_apb4,
  pready_wdg_slv_apb4,
  pslverr_wdg_slv_apb4,
  
// Instance: u_cd_clk_peri_25m, Port: chiplink_slv_axi4_tpv

  awid_chiplink_slv_axi4_tpv,
  awaddr_chiplink_slv_axi4_tpv,
  awlen_chiplink_slv_axi4_tpv,
  awsize_chiplink_slv_axi4_tpv,
  awburst_chiplink_slv_axi4_tpv,
  awlock_chiplink_slv_axi4_tpv,
  awcache_chiplink_slv_axi4_tpv,
  awprot_chiplink_slv_axi4_tpv,
  awvalid_chiplink_slv_axi4_tpv,
  awready_chiplink_slv_axi4_tpv,
  wdata_chiplink_slv_axi4_tpv,
  wstrb_chiplink_slv_axi4_tpv,
  wlast_chiplink_slv_axi4_tpv,
  wvalid_chiplink_slv_axi4_tpv,
  wready_chiplink_slv_axi4_tpv,
  bid_chiplink_slv_axi4_tpv,
  bresp_chiplink_slv_axi4_tpv,
  bvalid_chiplink_slv_axi4_tpv,
  bready_chiplink_slv_axi4_tpv,
  arid_chiplink_slv_axi4_tpv,
  araddr_chiplink_slv_axi4_tpv,
  arlen_chiplink_slv_axi4_tpv,
  arsize_chiplink_slv_axi4_tpv,
  arburst_chiplink_slv_axi4_tpv,
  arlock_chiplink_slv_axi4_tpv,
  arcache_chiplink_slv_axi4_tpv,
  arprot_chiplink_slv_axi4_tpv,
  arvalid_chiplink_slv_axi4_tpv,
  arready_chiplink_slv_axi4_tpv,
  rid_chiplink_slv_axi4_tpv,
  rdata_chiplink_slv_axi4_tpv,
  rresp_chiplink_slv_axi4_tpv,
  rlast_chiplink_slv_axi4_tpv,
  rvalid_chiplink_slv_axi4_tpv,
  rready_chiplink_slv_axi4_tpv,
  
// Instance: u_cd_clk_peri_25m, Port: dma_axi4_cpu_s

  awid_dma_axi4_cpu_s,
  awaddr_dma_axi4_cpu_s,
  awlen_dma_axi4_cpu_s,
  awsize_dma_axi4_cpu_s,
  awburst_dma_axi4_cpu_s,
  awlock_dma_axi4_cpu_s,
  awcache_dma_axi4_cpu_s,
  awprot_dma_axi4_cpu_s,
  awvalid_dma_axi4_cpu_s,
  awready_dma_axi4_cpu_s,
  wdata_dma_axi4_cpu_s,
  wstrb_dma_axi4_cpu_s,
  wlast_dma_axi4_cpu_s,
  wvalid_dma_axi4_cpu_s,
  wready_dma_axi4_cpu_s,
  bid_dma_axi4_cpu_s,
  bresp_dma_axi4_cpu_s,
  bvalid_dma_axi4_cpu_s,
  bready_dma_axi4_cpu_s,
  arid_dma_axi4_cpu_s,
  araddr_dma_axi4_cpu_s,
  arlen_dma_axi4_cpu_s,
  arsize_dma_axi4_cpu_s,
  arburst_dma_axi4_cpu_s,
  arlock_dma_axi4_cpu_s,
  arcache_dma_axi4_cpu_s,
  arprot_dma_axi4_cpu_s,
  arvalid_dma_axi4_cpu_s,
  arready_dma_axi4_cpu_s,
  rid_dma_axi4_cpu_s,
  rdata_dma_axi4_cpu_s,
  rresp_dma_axi4_cpu_s,
  rlast_dma_axi4_cpu_s,
  rvalid_dma_axi4_cpu_s,
  rready_dma_axi4_cpu_s,
  
// Instance: u_cd_clk_peri_25m, Port: spfs_slv_apb4_tpv

  paddr_spfs_slv_apb4_tpv,
  pselx_spfs_slv_apb4_tpv,
  penable_spfs_slv_apb4_tpv,
  pwrite_spfs_slv_apb4_tpv,
  prdata_spfs_slv_apb4_tpv,
  pwdata_spfs_slv_apb4_tpv,
  pprot_spfs_slv_apb4_tpv,
  pstrb_spfs_slv_apb4_tpv,
  pready_spfs_slv_apb4_tpv,
  pslverr_spfs_slv_apb4_tpv,
  
// Instance: u_cd_clk_peri_25m, Port: uart_slv_apb4_tpv

  paddr_uart_slv_apb4_tpv,
  pselx_uart_slv_apb4_tpv,
  penable_uart_slv_apb4_tpv,
  pwrite_uart_slv_apb4_tpv,
  prdata_uart_slv_apb4_tpv,
  pwdata_uart_slv_apb4_tpv,
  pprot_uart_slv_apb4_tpv,
  pstrb_uart_slv_apb4_tpv,
  pready_uart_slv_apb4_tpv,
  pslverr_uart_slv_apb4_tpv,

//  Non-bus signals

  clk_aud_12288kclk,
  clk_aud_12288kclken,
  clk_aud_12288kresetn,
  clk_core_200_800mclk,
  clk_core_200_800mresetn,
  clk_peri_100mclk,
  clk_peri_100mclken,
  clk_peri_100mresetn,
  clk_peri_25mclk,
  clk_peri_25mclken,
  clk_peri_25mresetn

);



//-----------------------------------------------------------------------------
// Port Declarations
//-----------------------------------------------------------------------------


// Instance: u_cd_clk_aud_12288k, Port: i2s_slv_apb4

output [31:0] paddr_i2s_slv_apb4;
output        pselx_i2s_slv_apb4;
output        penable_i2s_slv_apb4;
output        pwrite_i2s_slv_apb4;
input  [31:0] prdata_i2s_slv_apb4;
output [31:0] pwdata_i2s_slv_apb4;
output [2:0]  pprot_i2s_slv_apb4;
output [3:0]  pstrb_i2s_slv_apb4;
input         pready_i2s_slv_apb4;
input         pslverr_i2s_slv_apb4;

// Instance: u_cd_clk_core_200_800m, Port: cpu_mst_axi4

input  [2:0]  awid_cpu_mst_axi4;
input  [31:0] awaddr_cpu_mst_axi4;
input  [7:0]  awlen_cpu_mst_axi4;
input  [2:0]  awsize_cpu_mst_axi4;
input  [1:0]  awburst_cpu_mst_axi4;
input         awlock_cpu_mst_axi4;
input  [3:0]  awcache_cpu_mst_axi4;
input  [2:0]  awprot_cpu_mst_axi4;
input         awvalid_cpu_mst_axi4;
output        awready_cpu_mst_axi4;
input  [31:0] wdata_cpu_mst_axi4;
input  [3:0]  wstrb_cpu_mst_axi4;
input         wlast_cpu_mst_axi4;
input         wvalid_cpu_mst_axi4;
output        wready_cpu_mst_axi4;
output [2:0]  bid_cpu_mst_axi4;
output [1:0]  bresp_cpu_mst_axi4;
output        bvalid_cpu_mst_axi4;
input         bready_cpu_mst_axi4;
input  [2:0]  arid_cpu_mst_axi4;
input  [31:0] araddr_cpu_mst_axi4;
input  [7:0]  arlen_cpu_mst_axi4;
input  [2:0]  arsize_cpu_mst_axi4;
input  [1:0]  arburst_cpu_mst_axi4;
input         arlock_cpu_mst_axi4;
input  [3:0]  arcache_cpu_mst_axi4;
input  [2:0]  arprot_cpu_mst_axi4;
input         arvalid_cpu_mst_axi4;
output        arready_cpu_mst_axi4;
output [2:0]  rid_cpu_mst_axi4;
output [31:0] rdata_cpu_mst_axi4;
output [1:0]  rresp_cpu_mst_axi4;
output        rlast_cpu_mst_axi4;
output        rvalid_cpu_mst_axi4;
input         rready_cpu_mst_axi4;

// Instance: u_cd_clk_core_200_800m, Port: dma_axi4_cpu_m

output [3:0]  awid_dma_axi4_cpu_m;
output [31:0] awaddr_dma_axi4_cpu_m;
output [7:0]  awlen_dma_axi4_cpu_m;
output [2:0]  awsize_dma_axi4_cpu_m;
output [1:0]  awburst_dma_axi4_cpu_m;
output        awlock_dma_axi4_cpu_m;
output [3:0]  awcache_dma_axi4_cpu_m;
output [2:0]  awprot_dma_axi4_cpu_m;
output        awvalid_dma_axi4_cpu_m;
input         awready_dma_axi4_cpu_m;
output [31:0] wdata_dma_axi4_cpu_m;
output [3:0]  wstrb_dma_axi4_cpu_m;
output        wlast_dma_axi4_cpu_m;
output        wvalid_dma_axi4_cpu_m;
input         wready_dma_axi4_cpu_m;
input  [3:0]  bid_dma_axi4_cpu_m;
input  [1:0]  bresp_dma_axi4_cpu_m;
input         bvalid_dma_axi4_cpu_m;
output        bready_dma_axi4_cpu_m;
output [3:0]  arid_dma_axi4_cpu_m;
output [31:0] araddr_dma_axi4_cpu_m;
output [7:0]  arlen_dma_axi4_cpu_m;
output [2:0]  arsize_dma_axi4_cpu_m;
output [1:0]  arburst_dma_axi4_cpu_m;
output        arlock_dma_axi4_cpu_m;
output [3:0]  arcache_dma_axi4_cpu_m;
output [2:0]  arprot_dma_axi4_cpu_m;
output        arvalid_dma_axi4_cpu_m;
input         arready_dma_axi4_cpu_m;
input  [3:0]  rid_dma_axi4_cpu_m;
input  [31:0] rdata_dma_axi4_cpu_m;
input  [1:0]  rresp_dma_axi4_cpu_m;
input         rlast_dma_axi4_cpu_m;
input         rvalid_dma_axi4_cpu_m;
output        rready_dma_axi4_cpu_m;

// Instance: u_cd_clk_core_200_800m, Port: sram_slv_axi4

output [3:0]  awid_sram_slv_axi4;
output [31:0] awaddr_sram_slv_axi4;
output [7:0]  awlen_sram_slv_axi4;
output [2:0]  awsize_sram_slv_axi4;
output [1:0]  awburst_sram_slv_axi4;
output        awlock_sram_slv_axi4;
output [3:0]  awcache_sram_slv_axi4;
output [2:0]  awprot_sram_slv_axi4;
output        awvalid_sram_slv_axi4;
input         awready_sram_slv_axi4;
output [63:0] wdata_sram_slv_axi4;
output [7:0]  wstrb_sram_slv_axi4;
output        wlast_sram_slv_axi4;
output        wvalid_sram_slv_axi4;
input         wready_sram_slv_axi4;
input  [3:0]  bid_sram_slv_axi4;
input  [1:0]  bresp_sram_slv_axi4;
input         bvalid_sram_slv_axi4;
output        bready_sram_slv_axi4;
output [3:0]  arid_sram_slv_axi4;
output [31:0] araddr_sram_slv_axi4;
output [7:0]  arlen_sram_slv_axi4;
output [2:0]  arsize_sram_slv_axi4;
output [1:0]  arburst_sram_slv_axi4;
output        arlock_sram_slv_axi4;
output [3:0]  arcache_sram_slv_axi4;
output [2:0]  arprot_sram_slv_axi4;
output        arvalid_sram_slv_axi4;
input         arready_sram_slv_axi4;
input  [3:0]  rid_sram_slv_axi4;
input  [63:0] rdata_sram_slv_axi4;
input  [1:0]  rresp_sram_slv_axi4;
input         rlast_sram_slv_axi4;
input         rvalid_sram_slv_axi4;
output        rready_sram_slv_axi4;

// Instance: u_cd_clk_peri_100m, Port: archinfo_slv_apb4

output [31:0] paddr_archinfo_slv_apb4;
output        pselx_archinfo_slv_apb4;
output        penable_archinfo_slv_apb4;
output        pwrite_archinfo_slv_apb4;
input  [31:0] prdata_archinfo_slv_apb4;
output [31:0] pwdata_archinfo_slv_apb4;
output [2:0]  pprot_archinfo_slv_apb4;
output [3:0]  pstrb_archinfo_slv_apb4;
input         pready_archinfo_slv_apb4;
input         pslverr_archinfo_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: clint_slv_apb4

output [31:0] paddr_clint_slv_apb4;
output        pselx_clint_slv_apb4;
output        penable_clint_slv_apb4;
output        pwrite_clint_slv_apb4;
input  [31:0] prdata_clint_slv_apb4;
output [31:0] pwdata_clint_slv_apb4;
output [2:0]  pprot_clint_slv_apb4;
output [3:0]  pstrb_clint_slv_apb4;
input         pready_clint_slv_apb4;
input         pslverr_clint_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: crc_slv_apb4

output [31:0] paddr_crc_slv_apb4;
output        pselx_crc_slv_apb4;
output        penable_crc_slv_apb4;
output        pwrite_crc_slv_apb4;
input  [31:0] prdata_crc_slv_apb4;
output [31:0] pwdata_crc_slv_apb4;
output [2:0]  pprot_crc_slv_apb4;
output [3:0]  pstrb_crc_slv_apb4;
input         pready_crc_slv_apb4;
input         pslverr_crc_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: gpio_slv_apb4

output [31:0] paddr_gpio_slv_apb4;
output        pselx_gpio_slv_apb4;
output        penable_gpio_slv_apb4;
output        pwrite_gpio_slv_apb4;
input  [31:0] prdata_gpio_slv_apb4;
output [31:0] pwdata_gpio_slv_apb4;
output [2:0]  pprot_gpio_slv_apb4;
output [3:0]  pstrb_gpio_slv_apb4;
input         pready_gpio_slv_apb4;
input         pslverr_gpio_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: i2c_slv_apb4

output [31:0] paddr_i2c_slv_apb4;
output        pselx_i2c_slv_apb4;
output        penable_i2c_slv_apb4;
output        pwrite_i2c_slv_apb4;
input  [31:0] prdata_i2c_slv_apb4;
output [31:0] pwdata_i2c_slv_apb4;
output [2:0]  pprot_i2c_slv_apb4;
output [3:0]  pstrb_i2c_slv_apb4;
input         pready_i2c_slv_apb4;
input         pslverr_i2c_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: plic_slv_apb4

output [31:0] paddr_plic_slv_apb4;
output        pselx_plic_slv_apb4;
output        penable_plic_slv_apb4;
output        pwrite_plic_slv_apb4;
input  [31:0] prdata_plic_slv_apb4;
output [31:0] pwdata_plic_slv_apb4;
output [2:0]  pprot_plic_slv_apb4;
output [3:0]  pstrb_plic_slv_apb4;
input         pready_plic_slv_apb4;
input         pslverr_plic_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: ps2_slv_apb4

output [31:0] paddr_ps2_slv_apb4;
output        pselx_ps2_slv_apb4;
output        penable_ps2_slv_apb4;
output        pwrite_ps2_slv_apb4;
input  [31:0] prdata_ps2_slv_apb4;
output [31:0] pwdata_ps2_slv_apb4;
output [2:0]  pprot_ps2_slv_apb4;
output [3:0]  pstrb_ps2_slv_apb4;
input         pready_ps2_slv_apb4;
input         pslverr_ps2_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: psram_slv_apb4

output [31:0] paddr_psram_slv_apb4;
output        pselx_psram_slv_apb4;
output        penable_psram_slv_apb4;
output        pwrite_psram_slv_apb4;
input  [31:0] prdata_psram_slv_apb4;
output [31:0] pwdata_psram_slv_apb4;
output [2:0]  pprot_psram_slv_apb4;
output [3:0]  pstrb_psram_slv_apb4;
input         pready_psram_slv_apb4;
input         pslverr_psram_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: psram_slv_axi4

output [3:0]  awid_psram_slv_axi4;
output [31:0] awaddr_psram_slv_axi4;
output [7:0]  awlen_psram_slv_axi4;
output [2:0]  awsize_psram_slv_axi4;
output [1:0]  awburst_psram_slv_axi4;
output        awlock_psram_slv_axi4;
output [3:0]  awcache_psram_slv_axi4;
output [2:0]  awprot_psram_slv_axi4;
output        awvalid_psram_slv_axi4;
input         awready_psram_slv_axi4;
output [63:0] wdata_psram_slv_axi4;
output [7:0]  wstrb_psram_slv_axi4;
output        wlast_psram_slv_axi4;
output        wvalid_psram_slv_axi4;
input         wready_psram_slv_axi4;
input  [3:0]  bid_psram_slv_axi4;
input  [1:0]  bresp_psram_slv_axi4;
input         bvalid_psram_slv_axi4;
output        bready_psram_slv_axi4;
output [3:0]  arid_psram_slv_axi4;
output [31:0] araddr_psram_slv_axi4;
output [7:0]  arlen_psram_slv_axi4;
output [2:0]  arsize_psram_slv_axi4;
output [1:0]  arburst_psram_slv_axi4;
output        arlock_psram_slv_axi4;
output [3:0]  arcache_psram_slv_axi4;
output [2:0]  arprot_psram_slv_axi4;
output        arvalid_psram_slv_axi4;
input         arready_psram_slv_axi4;
input  [3:0]  rid_psram_slv_axi4;
input  [63:0] rdata_psram_slv_axi4;
input  [1:0]  rresp_psram_slv_axi4;
input         rlast_psram_slv_axi4;
input         rvalid_psram_slv_axi4;
output        rready_psram_slv_axi4;

// Instance: u_cd_clk_peri_100m, Port: pwm0_slv_apb4

output [31:0] paddr_pwm0_slv_apb4;
output        pselx_pwm0_slv_apb4;
output        penable_pwm0_slv_apb4;
output        pwrite_pwm0_slv_apb4;
input  [31:0] prdata_pwm0_slv_apb4;
output [31:0] pwdata_pwm0_slv_apb4;
output [2:0]  pprot_pwm0_slv_apb4;
output [3:0]  pstrb_pwm0_slv_apb4;
input         pready_pwm0_slv_apb4;
input         pslverr_pwm0_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: pwm1_slv_apb4

output [31:0] paddr_pwm1_slv_apb4;
output        pselx_pwm1_slv_apb4;
output        penable_pwm1_slv_apb4;
output        pwrite_pwm1_slv_apb4;
input  [31:0] prdata_pwm1_slv_apb4;
output [31:0] pwdata_pwm1_slv_apb4;
output [2:0]  pprot_pwm1_slv_apb4;
output [3:0]  pstrb_pwm1_slv_apb4;
input         pready_pwm1_slv_apb4;
input         pslverr_pwm1_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: pwm2_slv_apb4

output [31:0] paddr_pwm2_slv_apb4;
output        pselx_pwm2_slv_apb4;
output        penable_pwm2_slv_apb4;
output        pwrite_pwm2_slv_apb4;
input  [31:0] prdata_pwm2_slv_apb4;
output [31:0] pwdata_pwm2_slv_apb4;
output [2:0]  pprot_pwm2_slv_apb4;
output [3:0]  pstrb_pwm2_slv_apb4;
input         pready_pwm2_slv_apb4;
input         pslverr_pwm2_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: qspi_slv_apb4

output [31:0] paddr_qspi_slv_apb4;
output        pselx_qspi_slv_apb4;
output        penable_qspi_slv_apb4;
output        pwrite_qspi_slv_apb4;
input  [31:0] prdata_qspi_slv_apb4;
output [31:0] pwdata_qspi_slv_apb4;
output [2:0]  pprot_qspi_slv_apb4;
output [3:0]  pstrb_qspi_slv_apb4;
input         pready_qspi_slv_apb4;
input         pslverr_qspi_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: rcu_slv_apb4

output [31:0] paddr_rcu_slv_apb4;
output        pselx_rcu_slv_apb4;
output        penable_rcu_slv_apb4;
output        pwrite_rcu_slv_apb4;
input  [31:0] prdata_rcu_slv_apb4;
output [31:0] pwdata_rcu_slv_apb4;
output [2:0]  pprot_rcu_slv_apb4;
output [3:0]  pstrb_rcu_slv_apb4;
input         pready_rcu_slv_apb4;
input         pslverr_rcu_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: rng_slv_apb4

output [31:0] paddr_rng_slv_apb4;
output        pselx_rng_slv_apb4;
output        penable_rng_slv_apb4;
output        pwrite_rng_slv_apb4;
input  [31:0] prdata_rng_slv_apb4;
output [31:0] pwdata_rng_slv_apb4;
output [2:0]  pprot_rng_slv_apb4;
output [3:0]  pstrb_rng_slv_apb4;
input         pready_rng_slv_apb4;
input         pslverr_rng_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: rtc_slv_apb4

output [31:0] paddr_rtc_slv_apb4;
output        pselx_rtc_slv_apb4;
output        penable_rtc_slv_apb4;
output        pwrite_rtc_slv_apb4;
input  [31:0] prdata_rtc_slv_apb4;
output [31:0] pwdata_rtc_slv_apb4;
output [2:0]  pprot_rtc_slv_apb4;
output [3:0]  pstrb_rtc_slv_apb4;
input         pready_rtc_slv_apb4;
input         pslverr_rtc_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: sdram_slv_axi4

output [3:0]  awid_sdram_slv_axi4;
output [31:0] awaddr_sdram_slv_axi4;
output [7:0]  awlen_sdram_slv_axi4;
output [2:0]  awsize_sdram_slv_axi4;
output [1:0]  awburst_sdram_slv_axi4;
output        awlock_sdram_slv_axi4;
output [3:0]  awcache_sdram_slv_axi4;
output [2:0]  awprot_sdram_slv_axi4;
output        awvalid_sdram_slv_axi4;
input         awready_sdram_slv_axi4;
output [31:0] wdata_sdram_slv_axi4;
output [3:0]  wstrb_sdram_slv_axi4;
output        wlast_sdram_slv_axi4;
output        wvalid_sdram_slv_axi4;
input         wready_sdram_slv_axi4;
input  [3:0]  bid_sdram_slv_axi4;
input  [1:0]  bresp_sdram_slv_axi4;
input         bvalid_sdram_slv_axi4;
output        bready_sdram_slv_axi4;
output [3:0]  arid_sdram_slv_axi4;
output [31:0] araddr_sdram_slv_axi4;
output [7:0]  arlen_sdram_slv_axi4;
output [2:0]  arsize_sdram_slv_axi4;
output [1:0]  arburst_sdram_slv_axi4;
output        arlock_sdram_slv_axi4;
output [3:0]  arcache_sdram_slv_axi4;
output [2:0]  arprot_sdram_slv_axi4;
output        arvalid_sdram_slv_axi4;
input         arready_sdram_slv_axi4;
input  [3:0]  rid_sdram_slv_axi4;
input  [31:0] rdata_sdram_slv_axi4;
input  [1:0]  rresp_sdram_slv_axi4;
input         rlast_sdram_slv_axi4;
input         rvalid_sdram_slv_axi4;
output        rready_sdram_slv_axi4;

// Instance: u_cd_clk_peri_100m, Port: spi0_slv_apb4

output [31:0] paddr_spi0_slv_apb4;
output        pselx_spi0_slv_apb4;
output        penable_spi0_slv_apb4;
output        pwrite_spi0_slv_apb4;
input  [31:0] prdata_spi0_slv_apb4;
output [31:0] pwdata_spi0_slv_apb4;
output [2:0]  pprot_spi0_slv_apb4;
output [3:0]  pstrb_spi0_slv_apb4;
input         pready_spi0_slv_apb4;
input         pslverr_spi0_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: spi1_slv_apb4

output [31:0] paddr_spi1_slv_apb4;
output        pselx_spi1_slv_apb4;
output        penable_spi1_slv_apb4;
output        pwrite_spi1_slv_apb4;
input  [31:0] prdata_spi1_slv_apb4;
output [31:0] pwdata_spi1_slv_apb4;
output [2:0]  pprot_spi1_slv_apb4;
output [3:0]  pstrb_spi1_slv_apb4;
input         pready_spi1_slv_apb4;
input         pslverr_spi1_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: tim0_slv_apb4

output [31:0] paddr_tim0_slv_apb4;
output        pselx_tim0_slv_apb4;
output        penable_tim0_slv_apb4;
output        pwrite_tim0_slv_apb4;
input  [31:0] prdata_tim0_slv_apb4;
output [31:0] pwdata_tim0_slv_apb4;
output [2:0]  pprot_tim0_slv_apb4;
output [3:0]  pstrb_tim0_slv_apb4;
input         pready_tim0_slv_apb4;
input         pslverr_tim0_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: tim1_slv_apb4

output [31:0] paddr_tim1_slv_apb4;
output        pselx_tim1_slv_apb4;
output        penable_tim1_slv_apb4;
output        pwrite_tim1_slv_apb4;
input  [31:0] prdata_tim1_slv_apb4;
output [31:0] pwdata_tim1_slv_apb4;
output [2:0]  pprot_tim1_slv_apb4;
output [3:0]  pstrb_tim1_slv_apb4;
input         pready_tim1_slv_apb4;
input         pslverr_tim1_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: tim2_slv_apb4

output [31:0] paddr_tim2_slv_apb4;
output        pselx_tim2_slv_apb4;
output        penable_tim2_slv_apb4;
output        pwrite_tim2_slv_apb4;
input  [31:0] prdata_tim2_slv_apb4;
output [31:0] pwdata_tim2_slv_apb4;
output [2:0]  pprot_tim2_slv_apb4;
output [3:0]  pstrb_tim2_slv_apb4;
input         pready_tim2_slv_apb4;
input         pslverr_tim2_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: tim3_slv_apb4

output [31:0] paddr_tim3_slv_apb4;
output        pselx_tim3_slv_apb4;
output        penable_tim3_slv_apb4;
output        pwrite_tim3_slv_apb4;
input  [31:0] prdata_tim3_slv_apb4;
output [31:0] pwdata_tim3_slv_apb4;
output [2:0]  pprot_tim3_slv_apb4;
output [3:0]  pstrb_tim3_slv_apb4;
input         pready_tim3_slv_apb4;
input         pslverr_tim3_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: uart_slv_apb4

output [31:0] paddr_uart_slv_apb4;
output        pselx_uart_slv_apb4;
output        penable_uart_slv_apb4;
output        pwrite_uart_slv_apb4;
input  [31:0] prdata_uart_slv_apb4;
output [31:0] pwdata_uart_slv_apb4;
output [2:0]  pprot_uart_slv_apb4;
output [3:0]  pstrb_uart_slv_apb4;
input         pready_uart_slv_apb4;
input         pslverr_uart_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: vgalcd_mst_axi4

input  [2:0]  awid_vgalcd_mst_axi4;
input  [31:0] awaddr_vgalcd_mst_axi4;
input  [7:0]  awlen_vgalcd_mst_axi4;
input  [2:0]  awsize_vgalcd_mst_axi4;
input  [1:0]  awburst_vgalcd_mst_axi4;
input         awlock_vgalcd_mst_axi4;
input  [3:0]  awcache_vgalcd_mst_axi4;
input  [2:0]  awprot_vgalcd_mst_axi4;
input         awvalid_vgalcd_mst_axi4;
output        awready_vgalcd_mst_axi4;
input  [63:0] wdata_vgalcd_mst_axi4;
input  [7:0]  wstrb_vgalcd_mst_axi4;
input         wlast_vgalcd_mst_axi4;
input         wvalid_vgalcd_mst_axi4;
output        wready_vgalcd_mst_axi4;
output [2:0]  bid_vgalcd_mst_axi4;
output [1:0]  bresp_vgalcd_mst_axi4;
output        bvalid_vgalcd_mst_axi4;
input         bready_vgalcd_mst_axi4;
input  [2:0]  arid_vgalcd_mst_axi4;
input  [31:0] araddr_vgalcd_mst_axi4;
input  [7:0]  arlen_vgalcd_mst_axi4;
input  [2:0]  arsize_vgalcd_mst_axi4;
input  [1:0]  arburst_vgalcd_mst_axi4;
input         arlock_vgalcd_mst_axi4;
input  [3:0]  arcache_vgalcd_mst_axi4;
input  [2:0]  arprot_vgalcd_mst_axi4;
input         arvalid_vgalcd_mst_axi4;
output        arready_vgalcd_mst_axi4;
output [2:0]  rid_vgalcd_mst_axi4;
output [63:0] rdata_vgalcd_mst_axi4;
output [1:0]  rresp_vgalcd_mst_axi4;
output        rlast_vgalcd_mst_axi4;
output        rvalid_vgalcd_mst_axi4;
input         rready_vgalcd_mst_axi4;

// Instance: u_cd_clk_peri_100m, Port: vgalcd_slv_apb4

output [31:0] paddr_vgalcd_slv_apb4;
output        pselx_vgalcd_slv_apb4;
output        penable_vgalcd_slv_apb4;
output        pwrite_vgalcd_slv_apb4;
input  [31:0] prdata_vgalcd_slv_apb4;
output [31:0] pwdata_vgalcd_slv_apb4;
output [2:0]  pprot_vgalcd_slv_apb4;
output [3:0]  pstrb_vgalcd_slv_apb4;
input         pready_vgalcd_slv_apb4;
input         pslverr_vgalcd_slv_apb4;

// Instance: u_cd_clk_peri_100m, Port: wdg_slv_apb4

output [31:0] paddr_wdg_slv_apb4;
output        pselx_wdg_slv_apb4;
output        penable_wdg_slv_apb4;
output        pwrite_wdg_slv_apb4;
input  [31:0] prdata_wdg_slv_apb4;
output [31:0] pwdata_wdg_slv_apb4;
output [2:0]  pprot_wdg_slv_apb4;
output [3:0]  pstrb_wdg_slv_apb4;
input         pready_wdg_slv_apb4;
input         pslverr_wdg_slv_apb4;

// Instance: u_cd_clk_peri_25m, Port: chiplink_slv_axi4_tpv

output [3:0]  awid_chiplink_slv_axi4_tpv;
output [31:0] awaddr_chiplink_slv_axi4_tpv;
output [7:0]  awlen_chiplink_slv_axi4_tpv;
output [2:0]  awsize_chiplink_slv_axi4_tpv;
output [1:0]  awburst_chiplink_slv_axi4_tpv;
output        awlock_chiplink_slv_axi4_tpv;
output [3:0]  awcache_chiplink_slv_axi4_tpv;
output [2:0]  awprot_chiplink_slv_axi4_tpv;
output        awvalid_chiplink_slv_axi4_tpv;
input         awready_chiplink_slv_axi4_tpv;
output [63:0] wdata_chiplink_slv_axi4_tpv;
output [7:0]  wstrb_chiplink_slv_axi4_tpv;
output        wlast_chiplink_slv_axi4_tpv;
output        wvalid_chiplink_slv_axi4_tpv;
input         wready_chiplink_slv_axi4_tpv;
input  [3:0]  bid_chiplink_slv_axi4_tpv;
input  [1:0]  bresp_chiplink_slv_axi4_tpv;
input         bvalid_chiplink_slv_axi4_tpv;
output        bready_chiplink_slv_axi4_tpv;
output [3:0]  arid_chiplink_slv_axi4_tpv;
output [31:0] araddr_chiplink_slv_axi4_tpv;
output [7:0]  arlen_chiplink_slv_axi4_tpv;
output [2:0]  arsize_chiplink_slv_axi4_tpv;
output [1:0]  arburst_chiplink_slv_axi4_tpv;
output        arlock_chiplink_slv_axi4_tpv;
output [3:0]  arcache_chiplink_slv_axi4_tpv;
output [2:0]  arprot_chiplink_slv_axi4_tpv;
output        arvalid_chiplink_slv_axi4_tpv;
input         arready_chiplink_slv_axi4_tpv;
input  [3:0]  rid_chiplink_slv_axi4_tpv;
input  [63:0] rdata_chiplink_slv_axi4_tpv;
input  [1:0]  rresp_chiplink_slv_axi4_tpv;
input         rlast_chiplink_slv_axi4_tpv;
input         rvalid_chiplink_slv_axi4_tpv;
output        rready_chiplink_slv_axi4_tpv;

// Instance: u_cd_clk_peri_25m, Port: dma_axi4_cpu_s

input  [3:0]  awid_dma_axi4_cpu_s;
input  [31:0] awaddr_dma_axi4_cpu_s;
input  [7:0]  awlen_dma_axi4_cpu_s;
input  [2:0]  awsize_dma_axi4_cpu_s;
input  [1:0]  awburst_dma_axi4_cpu_s;
input         awlock_dma_axi4_cpu_s;
input  [3:0]  awcache_dma_axi4_cpu_s;
input  [2:0]  awprot_dma_axi4_cpu_s;
input         awvalid_dma_axi4_cpu_s;
output        awready_dma_axi4_cpu_s;
input  [63:0] wdata_dma_axi4_cpu_s;
input  [7:0]  wstrb_dma_axi4_cpu_s;
input         wlast_dma_axi4_cpu_s;
input         wvalid_dma_axi4_cpu_s;
output        wready_dma_axi4_cpu_s;
output [3:0]  bid_dma_axi4_cpu_s;
output [1:0]  bresp_dma_axi4_cpu_s;
output        bvalid_dma_axi4_cpu_s;
input         bready_dma_axi4_cpu_s;
input  [3:0]  arid_dma_axi4_cpu_s;
input  [31:0] araddr_dma_axi4_cpu_s;
input  [7:0]  arlen_dma_axi4_cpu_s;
input  [2:0]  arsize_dma_axi4_cpu_s;
input  [1:0]  arburst_dma_axi4_cpu_s;
input         arlock_dma_axi4_cpu_s;
input  [3:0]  arcache_dma_axi4_cpu_s;
input  [2:0]  arprot_dma_axi4_cpu_s;
input         arvalid_dma_axi4_cpu_s;
output        arready_dma_axi4_cpu_s;
output [3:0]  rid_dma_axi4_cpu_s;
output [63:0] rdata_dma_axi4_cpu_s;
output [1:0]  rresp_dma_axi4_cpu_s;
output        rlast_dma_axi4_cpu_s;
output        rvalid_dma_axi4_cpu_s;
input         rready_dma_axi4_cpu_s;

// Instance: u_cd_clk_peri_25m, Port: spfs_slv_apb4_tpv

output [31:0] paddr_spfs_slv_apb4_tpv;
output        pselx_spfs_slv_apb4_tpv;
output        penable_spfs_slv_apb4_tpv;
output        pwrite_spfs_slv_apb4_tpv;
input  [31:0] prdata_spfs_slv_apb4_tpv;
output [31:0] pwdata_spfs_slv_apb4_tpv;
output [2:0]  pprot_spfs_slv_apb4_tpv;
output [3:0]  pstrb_spfs_slv_apb4_tpv;
input         pready_spfs_slv_apb4_tpv;
input         pslverr_spfs_slv_apb4_tpv;

// Instance: u_cd_clk_peri_25m, Port: uart_slv_apb4_tpv

output [31:0] paddr_uart_slv_apb4_tpv;
output        pselx_uart_slv_apb4_tpv;
output        penable_uart_slv_apb4_tpv;
output        pwrite_uart_slv_apb4_tpv;
input  [31:0] prdata_uart_slv_apb4_tpv;
output [31:0] pwdata_uart_slv_apb4_tpv;
output [2:0]  pprot_uart_slv_apb4_tpv;
output [3:0]  pstrb_uart_slv_apb4_tpv;
input         pready_uart_slv_apb4_tpv;
input         pslverr_uart_slv_apb4_tpv;

//  Non-bus signals

input         clk_aud_12288kclk;
input         clk_aud_12288kclken;
input         clk_aud_12288kresetn;
input         clk_core_200_800mclk;
input         clk_core_200_800mresetn;
input         clk_peri_100mclk;
input         clk_peri_100mclken;
input         clk_peri_100mresetn;
input         clk_peri_25mclk;
input         clk_peri_25mclken;
input         clk_peri_25mresetn;



//-----------------------------------------------------------------------------
// Internal Wire Declarations
//-----------------------------------------------------------------------------

wire   [31:0]  araddr_chiplink_slv_axi4_tpv;
wire   [31:0]  araddr_dma_axi4_cpu_m;
wire   [31:0]  araddr_psram_slv_axi4;
wire   [31:0]  araddr_sdram_slv_axi4;
wire   [31:0]  araddr_sram_slv_axi4;
wire   [1:0]   arburst_chiplink_slv_axi4_tpv;
wire   [1:0]   arburst_dma_axi4_cpu_m;
wire   [1:0]   arburst_psram_slv_axi4;
wire   [1:0]   arburst_sdram_slv_axi4;
wire   [1:0]   arburst_sram_slv_axi4;
wire   [3:0]   arcache_chiplink_slv_axi4_tpv;
wire   [3:0]   arcache_dma_axi4_cpu_m;
wire   [3:0]   arcache_psram_slv_axi4;
wire   [3:0]   arcache_sdram_slv_axi4;
wire   [3:0]   arcache_sram_slv_axi4;
wire   [3:0]   arid_chiplink_slv_axi4_tpv;
wire   [3:0]   arid_dma_axi4_cpu_m;
wire   [3:0]   arid_psram_slv_axi4;
wire   [3:0]   arid_sdram_slv_axi4;
wire   [3:0]   arid_sram_slv_axi4;
wire   [7:0]   arlen_chiplink_slv_axi4_tpv;
wire   [7:0]   arlen_dma_axi4_cpu_m;
wire   [7:0]   arlen_psram_slv_axi4;
wire   [7:0]   arlen_sdram_slv_axi4;
wire   [7:0]   arlen_sram_slv_axi4;
wire           arlock_chiplink_slv_axi4_tpv;
wire           arlock_dma_axi4_cpu_m;
wire           arlock_psram_slv_axi4;
wire           arlock_sdram_slv_axi4;
wire           arlock_sram_slv_axi4;
wire   [2:0]   arprot_chiplink_slv_axi4_tpv;
wire   [2:0]   arprot_dma_axi4_cpu_m;
wire   [2:0]   arprot_psram_slv_axi4;
wire   [2:0]   arprot_sdram_slv_axi4;
wire   [2:0]   arprot_sram_slv_axi4;
wire           arready_cpu_mst_axi4;
wire           arready_dma_axi4_cpu_s;
wire           arready_vgalcd_mst_axi4;
wire   [2:0]   arsize_chiplink_slv_axi4_tpv;
wire   [2:0]   arsize_dma_axi4_cpu_m;
wire   [2:0]   arsize_psram_slv_axi4;
wire   [2:0]   arsize_sdram_slv_axi4;
wire   [2:0]   arsize_sram_slv_axi4;
wire           arvalid_chiplink_slv_axi4_tpv;
wire           arvalid_dma_axi4_cpu_m;
wire           arvalid_psram_slv_axi4;
wire           arvalid_sdram_slv_axi4;
wire           arvalid_sram_slv_axi4;
wire   [31:0]  awaddr_chiplink_slv_axi4_tpv;
wire   [31:0]  awaddr_dma_axi4_cpu_m;
wire   [31:0]  awaddr_psram_slv_axi4;
wire   [31:0]  awaddr_sdram_slv_axi4;
wire   [31:0]  awaddr_sram_slv_axi4;
wire   [1:0]   awburst_chiplink_slv_axi4_tpv;
wire   [1:0]   awburst_dma_axi4_cpu_m;
wire   [1:0]   awburst_psram_slv_axi4;
wire   [1:0]   awburst_sdram_slv_axi4;
wire   [1:0]   awburst_sram_slv_axi4;
wire   [3:0]   awcache_chiplink_slv_axi4_tpv;
wire   [3:0]   awcache_dma_axi4_cpu_m;
wire   [3:0]   awcache_psram_slv_axi4;
wire   [3:0]   awcache_sdram_slv_axi4;
wire   [3:0]   awcache_sram_slv_axi4;
wire   [3:0]   awid_chiplink_slv_axi4_tpv;
wire   [3:0]   awid_dma_axi4_cpu_m;
wire   [3:0]   awid_psram_slv_axi4;
wire   [3:0]   awid_sdram_slv_axi4;
wire   [3:0]   awid_sram_slv_axi4;
wire   [7:0]   awlen_chiplink_slv_axi4_tpv;
wire   [7:0]   awlen_dma_axi4_cpu_m;
wire   [7:0]   awlen_psram_slv_axi4;
wire   [7:0]   awlen_sdram_slv_axi4;
wire   [7:0]   awlen_sram_slv_axi4;
wire           awlock_chiplink_slv_axi4_tpv;
wire           awlock_dma_axi4_cpu_m;
wire           awlock_psram_slv_axi4;
wire           awlock_sdram_slv_axi4;
wire           awlock_sram_slv_axi4;
wire   [2:0]   awprot_chiplink_slv_axi4_tpv;
wire   [2:0]   awprot_dma_axi4_cpu_m;
wire   [2:0]   awprot_psram_slv_axi4;
wire   [2:0]   awprot_sdram_slv_axi4;
wire   [2:0]   awprot_sram_slv_axi4;
wire           awready_cpu_mst_axi4;
wire           awready_dma_axi4_cpu_s;
wire           awready_vgalcd_mst_axi4;
wire   [2:0]   awsize_chiplink_slv_axi4_tpv;
wire   [2:0]   awsize_dma_axi4_cpu_m;
wire   [2:0]   awsize_psram_slv_axi4;
wire   [2:0]   awsize_sdram_slv_axi4;
wire   [2:0]   awsize_sram_slv_axi4;
wire           awvalid_chiplink_slv_axi4_tpv;
wire           awvalid_dma_axi4_cpu_m;
wire           awvalid_psram_slv_axi4;
wire           awvalid_sdram_slv_axi4;
wire           awvalid_sram_slv_axi4;
wire   [2:0]   bid_cpu_mst_axi4;
wire   [3:0]   bid_dma_axi4_cpu_s;
wire   [2:0]   bid_vgalcd_mst_axi4;
wire           bready_chiplink_slv_axi4_tpv;
wire           bready_dma_axi4_cpu_m;
wire           bready_psram_slv_axi4;
wire           bready_sdram_slv_axi4;
wire           bready_sram_slv_axi4;
wire   [1:0]   bresp_cpu_mst_axi4;
wire   [1:0]   bresp_dma_axi4_cpu_s;
wire   [1:0]   bresp_vgalcd_mst_axi4;
wire           bvalid_cpu_mst_axi4;
wire           bvalid_dma_axi4_cpu_s;
wire           bvalid_vgalcd_mst_axi4;
wire   [31:0]  paddr_archinfo_slv_apb4;
wire   [31:0]  paddr_clint_slv_apb4;
wire   [31:0]  paddr_crc_slv_apb4;
wire   [31:0]  paddr_gpio_slv_apb4;
wire   [31:0]  paddr_i2c_slv_apb4;
wire   [31:0]  paddr_i2s_slv_apb4;
wire   [31:0]  paddr_plic_slv_apb4;
wire   [31:0]  paddr_ps2_slv_apb4;
wire   [31:0]  paddr_psram_slv_apb4;
wire   [31:0]  paddr_pwm0_slv_apb4;
wire   [31:0]  paddr_pwm1_slv_apb4;
wire   [31:0]  paddr_pwm2_slv_apb4;
wire   [31:0]  paddr_qspi_slv_apb4;
wire   [31:0]  paddr_rcu_slv_apb4;
wire   [31:0]  paddr_rng_slv_apb4;
wire   [31:0]  paddr_rtc_slv_apb4;
wire   [31:0]  paddr_spfs_slv_apb4_tpv;
wire   [31:0]  paddr_spi0_slv_apb4;
wire   [31:0]  paddr_spi1_slv_apb4;
wire   [31:0]  paddr_tim0_slv_apb4;
wire   [31:0]  paddr_tim1_slv_apb4;
wire   [31:0]  paddr_tim2_slv_apb4;
wire   [31:0]  paddr_tim3_slv_apb4;
wire   [31:0]  paddr_uart_slv_apb4;
wire   [31:0]  paddr_uart_slv_apb4_tpv;
wire   [31:0]  paddr_vgalcd_slv_apb4;
wire   [31:0]  paddr_wdg_slv_apb4;
wire           penable_archinfo_slv_apb4;
wire           penable_clint_slv_apb4;
wire           penable_crc_slv_apb4;
wire           penable_gpio_slv_apb4;
wire           penable_i2c_slv_apb4;
wire           penable_i2s_slv_apb4;
wire           penable_plic_slv_apb4;
wire           penable_ps2_slv_apb4;
wire           penable_psram_slv_apb4;
wire           penable_pwm0_slv_apb4;
wire           penable_pwm1_slv_apb4;
wire           penable_pwm2_slv_apb4;
wire           penable_qspi_slv_apb4;
wire           penable_rcu_slv_apb4;
wire           penable_rng_slv_apb4;
wire           penable_rtc_slv_apb4;
wire           penable_spfs_slv_apb4_tpv;
wire           penable_spi0_slv_apb4;
wire           penable_spi1_slv_apb4;
wire           penable_tim0_slv_apb4;
wire           penable_tim1_slv_apb4;
wire           penable_tim2_slv_apb4;
wire           penable_tim3_slv_apb4;
wire           penable_uart_slv_apb4;
wire           penable_uart_slv_apb4_tpv;
wire           penable_vgalcd_slv_apb4;
wire           penable_wdg_slv_apb4;
wire   [2:0]   pprot_archinfo_slv_apb4;
wire   [2:0]   pprot_clint_slv_apb4;
wire   [2:0]   pprot_crc_slv_apb4;
wire   [2:0]   pprot_gpio_slv_apb4;
wire   [2:0]   pprot_i2c_slv_apb4;
wire   [2:0]   pprot_i2s_slv_apb4;
wire   [2:0]   pprot_plic_slv_apb4;
wire   [2:0]   pprot_ps2_slv_apb4;
wire   [2:0]   pprot_psram_slv_apb4;
wire   [2:0]   pprot_pwm0_slv_apb4;
wire   [2:0]   pprot_pwm1_slv_apb4;
wire   [2:0]   pprot_pwm2_slv_apb4;
wire   [2:0]   pprot_qspi_slv_apb4;
wire   [2:0]   pprot_rcu_slv_apb4;
wire   [2:0]   pprot_rng_slv_apb4;
wire   [2:0]   pprot_rtc_slv_apb4;
wire   [2:0]   pprot_spfs_slv_apb4_tpv;
wire   [2:0]   pprot_spi0_slv_apb4;
wire   [2:0]   pprot_spi1_slv_apb4;
wire   [2:0]   pprot_tim0_slv_apb4;
wire   [2:0]   pprot_tim1_slv_apb4;
wire   [2:0]   pprot_tim2_slv_apb4;
wire   [2:0]   pprot_tim3_slv_apb4;
wire   [2:0]   pprot_uart_slv_apb4;
wire   [2:0]   pprot_uart_slv_apb4_tpv;
wire   [2:0]   pprot_vgalcd_slv_apb4;
wire   [2:0]   pprot_wdg_slv_apb4;
wire           pselx_archinfo_slv_apb4;
wire           pselx_clint_slv_apb4;
wire           pselx_crc_slv_apb4;
wire           pselx_gpio_slv_apb4;
wire           pselx_i2c_slv_apb4;
wire           pselx_i2s_slv_apb4;
wire           pselx_plic_slv_apb4;
wire           pselx_ps2_slv_apb4;
wire           pselx_psram_slv_apb4;
wire           pselx_pwm0_slv_apb4;
wire           pselx_pwm1_slv_apb4;
wire           pselx_pwm2_slv_apb4;
wire           pselx_qspi_slv_apb4;
wire           pselx_rcu_slv_apb4;
wire           pselx_rng_slv_apb4;
wire           pselx_rtc_slv_apb4;
wire           pselx_spfs_slv_apb4_tpv;
wire           pselx_spi0_slv_apb4;
wire           pselx_spi1_slv_apb4;
wire           pselx_tim0_slv_apb4;
wire           pselx_tim1_slv_apb4;
wire           pselx_tim2_slv_apb4;
wire           pselx_tim3_slv_apb4;
wire           pselx_uart_slv_apb4;
wire           pselx_uart_slv_apb4_tpv;
wire           pselx_vgalcd_slv_apb4;
wire           pselx_wdg_slv_apb4;
wire   [3:0]   pstrb_archinfo_slv_apb4;
wire   [3:0]   pstrb_clint_slv_apb4;
wire   [3:0]   pstrb_crc_slv_apb4;
wire   [3:0]   pstrb_gpio_slv_apb4;
wire   [3:0]   pstrb_i2c_slv_apb4;
wire   [3:0]   pstrb_i2s_slv_apb4;
wire   [3:0]   pstrb_plic_slv_apb4;
wire   [3:0]   pstrb_ps2_slv_apb4;
wire   [3:0]   pstrb_psram_slv_apb4;
wire   [3:0]   pstrb_pwm0_slv_apb4;
wire   [3:0]   pstrb_pwm1_slv_apb4;
wire   [3:0]   pstrb_pwm2_slv_apb4;
wire   [3:0]   pstrb_qspi_slv_apb4;
wire   [3:0]   pstrb_rcu_slv_apb4;
wire   [3:0]   pstrb_rng_slv_apb4;
wire   [3:0]   pstrb_rtc_slv_apb4;
wire   [3:0]   pstrb_spfs_slv_apb4_tpv;
wire   [3:0]   pstrb_spi0_slv_apb4;
wire   [3:0]   pstrb_spi1_slv_apb4;
wire   [3:0]   pstrb_tim0_slv_apb4;
wire   [3:0]   pstrb_tim1_slv_apb4;
wire   [3:0]   pstrb_tim2_slv_apb4;
wire   [3:0]   pstrb_tim3_slv_apb4;
wire   [3:0]   pstrb_uart_slv_apb4;
wire   [3:0]   pstrb_uart_slv_apb4_tpv;
wire   [3:0]   pstrb_vgalcd_slv_apb4;
wire   [3:0]   pstrb_wdg_slv_apb4;
wire   [31:0]  pwdata_archinfo_slv_apb4;
wire   [31:0]  pwdata_clint_slv_apb4;
wire   [31:0]  pwdata_crc_slv_apb4;
wire   [31:0]  pwdata_gpio_slv_apb4;
wire   [31:0]  pwdata_i2c_slv_apb4;
wire   [31:0]  pwdata_i2s_slv_apb4;
wire   [31:0]  pwdata_plic_slv_apb4;
wire   [31:0]  pwdata_ps2_slv_apb4;
wire   [31:0]  pwdata_psram_slv_apb4;
wire   [31:0]  pwdata_pwm0_slv_apb4;
wire   [31:0]  pwdata_pwm1_slv_apb4;
wire   [31:0]  pwdata_pwm2_slv_apb4;
wire   [31:0]  pwdata_qspi_slv_apb4;
wire   [31:0]  pwdata_rcu_slv_apb4;
wire   [31:0]  pwdata_rng_slv_apb4;
wire   [31:0]  pwdata_rtc_slv_apb4;
wire   [31:0]  pwdata_spfs_slv_apb4_tpv;
wire   [31:0]  pwdata_spi0_slv_apb4;
wire   [31:0]  pwdata_spi1_slv_apb4;
wire   [31:0]  pwdata_tim0_slv_apb4;
wire   [31:0]  pwdata_tim1_slv_apb4;
wire   [31:0]  pwdata_tim2_slv_apb4;
wire   [31:0]  pwdata_tim3_slv_apb4;
wire   [31:0]  pwdata_uart_slv_apb4;
wire   [31:0]  pwdata_uart_slv_apb4_tpv;
wire   [31:0]  pwdata_vgalcd_slv_apb4;
wire   [31:0]  pwdata_wdg_slv_apb4;
wire           pwrite_archinfo_slv_apb4;
wire           pwrite_clint_slv_apb4;
wire           pwrite_crc_slv_apb4;
wire           pwrite_gpio_slv_apb4;
wire           pwrite_i2c_slv_apb4;
wire           pwrite_i2s_slv_apb4;
wire           pwrite_plic_slv_apb4;
wire           pwrite_ps2_slv_apb4;
wire           pwrite_psram_slv_apb4;
wire           pwrite_pwm0_slv_apb4;
wire           pwrite_pwm1_slv_apb4;
wire           pwrite_pwm2_slv_apb4;
wire           pwrite_qspi_slv_apb4;
wire           pwrite_rcu_slv_apb4;
wire           pwrite_rng_slv_apb4;
wire           pwrite_rtc_slv_apb4;
wire           pwrite_spfs_slv_apb4_tpv;
wire           pwrite_spi0_slv_apb4;
wire           pwrite_spi1_slv_apb4;
wire           pwrite_tim0_slv_apb4;
wire           pwrite_tim1_slv_apb4;
wire           pwrite_tim2_slv_apb4;
wire           pwrite_tim3_slv_apb4;
wire           pwrite_uart_slv_apb4;
wire           pwrite_uart_slv_apb4_tpv;
wire           pwrite_vgalcd_slv_apb4;
wire           pwrite_wdg_slv_apb4;
wire   [31:0]  rdata_cpu_mst_axi4;
wire   [63:0]  rdata_dma_axi4_cpu_s;
wire   [63:0]  rdata_vgalcd_mst_axi4;
wire   [2:0]   rid_cpu_mst_axi4;
wire   [3:0]   rid_dma_axi4_cpu_s;
wire   [2:0]   rid_vgalcd_mst_axi4;
wire           rlast_cpu_mst_axi4;
wire           rlast_dma_axi4_cpu_s;
wire           rlast_vgalcd_mst_axi4;
wire           rready_chiplink_slv_axi4_tpv;
wire           rready_dma_axi4_cpu_m;
wire           rready_psram_slv_axi4;
wire           rready_sdram_slv_axi4;
wire           rready_sram_slv_axi4;
wire   [1:0]   rresp_cpu_mst_axi4;
wire   [1:0]   rresp_dma_axi4_cpu_s;
wire   [1:0]   rresp_vgalcd_mst_axi4;
wire           rvalid_cpu_mst_axi4;
wire           rvalid_dma_axi4_cpu_s;
wire           rvalid_vgalcd_mst_axi4;
wire   [63:0]  wdata_chiplink_slv_axi4_tpv;
wire   [31:0]  wdata_dma_axi4_cpu_m;
wire   [63:0]  wdata_psram_slv_axi4;
wire   [31:0]  wdata_sdram_slv_axi4;
wire   [63:0]  wdata_sram_slv_axi4;
wire           wlast_chiplink_slv_axi4_tpv;
wire           wlast_dma_axi4_cpu_m;
wire           wlast_psram_slv_axi4;
wire           wlast_sdram_slv_axi4;
wire           wlast_sram_slv_axi4;
wire           wready_cpu_mst_axi4;
wire           wready_dma_axi4_cpu_s;
wire           wready_vgalcd_mst_axi4;
wire   [7:0]   wstrb_chiplink_slv_axi4_tpv;
wire   [3:0]   wstrb_dma_axi4_cpu_m;
wire   [7:0]   wstrb_psram_slv_axi4;
wire   [3:0]   wstrb_sdram_slv_axi4;
wire   [7:0]   wstrb_sram_slv_axi4;
wire           wvalid_chiplink_slv_axi4_tpv;
wire           wvalid_dma_axi4_cpu_m;
wire           wvalid_psram_slv_axi4;
wire           wvalid_sdram_slv_axi4;
wire           wvalid_sram_slv_axi4;
wire           pack_tpv_gp_apb4_i2s_slv_apb4_int_async;    //i2s_slv_apb4_int_master_async - u_cd_clk_aud_12288k
wire   [32:0]  prevpayld_tpv_gp_apb4_i2s_slv_apb4_int_async;    //i2s_slv_apb4_int_master_async - u_cd_clk_aud_12288k
wire   [61:0]  a_data_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [61:0]  a_data_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [61:0]  a_data_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [61:0]  a_data_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   a_wpntr_gry_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   a_wpntr_gry_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   a_wpntr_gry_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   a_wpntr_gry_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [60:0]  ar_data_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [60:0]  ar_data_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [60:0]  ar_data_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           ar_rpntr_bin_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire           ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   ar_rpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   ar_wpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   ar_wpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [60:0]  aw_data_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [60:0]  aw_data_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [60:0]  aw_data_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           aw_rpntr_bin_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire           aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   aw_rpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   aw_wpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   aw_wpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [5:0]   b_data_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [4:0]   b_data_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire           b_rpntr_bin_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           b_rpntr_bin_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   b_rpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   b_rpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   b_wpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   b_wpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           d_rpntr_bin_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire           d_rpntr_bin_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire           d_rpntr_bin_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire           d_rpntr_bin_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   d_rpntr_gry_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   d_rpntr_gry_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   d_rpntr_gry_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   d_rpntr_gry_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [72:0]  r_data_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [71:0]  r_data_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire           r_rpntr_bin_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire           r_rpntr_bin_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   r_rpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   r_rpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   r_wpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   r_wpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [72:0]  w_data_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [36:0]  w_data_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [36:0]  w_data_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [72:0]  w_data_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [36:0]  w_data_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [36:0]  w_data_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [36:0]  w_data_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire           w_rpntr_bin_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire           w_rpntr_bin_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_rpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_rpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire   [1:0]   w_wpntr_gry_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_core_200_800m
wire           a_rpntr_bin_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire           a_rpntr_bin_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire           a_rpntr_bin_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   a_rpntr_gry_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   a_rpntr_gry_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   a_rpntr_gry_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [75:0]  ar_data_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire           ar_rpntr_bin_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire           ar_rpntr_bin_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   ar_rpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   ar_rpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [64:0]  aw_data_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire           aw_rpntr_bin_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire           aw_rpntr_bin_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   aw_rpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   aw_rpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [5:0]   b_data_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [5:0]   b_data_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire           b_rpntr_bin_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   b_rpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   b_wpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   b_wpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [39:0]  d_data_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [39:0]  d_data_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [39:0]  d_data_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   d_wpntr_gry_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   d_wpntr_gry_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   d_wpntr_gry_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [70:0]  r_data_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [38:0]  r_data_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire           r_rpntr_bin_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   r_rpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   r_wpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   r_wpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [72:0]  w_data_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire           w_rpntr_bin_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire           w_rpntr_bin_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire           w_rpntr_bin_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire           w_rpntr_bin_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire           w_rpntr_bin_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   w_rpntr_gry_perip0_gp_apb4_ib_int_async;    //perip0_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   w_rpntr_gry_perip1_gp_apb4_ib_int_async;    //perip1_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   w_rpntr_gry_psram_slv_axi4_ib_int_async;    //psram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   w_rpntr_gry_sdram_slv_axi4_ib_int_async;    //sdram_slv_axi4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   w_rpntr_gry_sys_gp_apb4_ib_int_async;    //sys_gp_apb4_ib_int_async - u_cd_clk_peri_100m
wire   [1:0]   w_wpntr_gry_vgalcd_mst_axi4_ib_int_async;    //vgalcd_mst_axi4_ib_int_async - u_cd_clk_peri_100m
wire           a_rpntr_bin_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   a_rpntr_gry_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_peri_25m
wire   [68:0]  ar_data_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire           ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   ar_wpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [57:0]  aw_data_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire           aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   aw_wpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [5:0]   b_data_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire           b_rpntr_bin_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   b_rpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [39:0]  d_data_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   d_wpntr_gry_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_peri_25m
wire   [71:0]  pfwdpayld_tpv_gp_apb4_i2s_slv_apb4_int_async;    //i2s_slv_apb4_int_slave_async - u_cd_clk_peri_25m
wire           preq_tpv_gp_apb4_i2s_slv_apb4_int_async;    //i2s_slv_apb4_int_slave_async - u_cd_clk_peri_25m
wire   [70:0]  r_data_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire           r_rpntr_bin_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   r_rpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [72:0]  w_data_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire           w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire           w_rpntr_bin_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async;    //chiplink_slv_axi4_tpv_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   w_rpntr_gry_tpv_gp_apb4_ib_int_async;    //tpv_gp_apb4_ib_int_async - u_cd_clk_peri_25m
wire   [1:0]   w_wpntr_gry_dma_axi4_cpu_ib_int_async;    //dma_axi4_cpu_ib_int_async - u_cd_clk_peri_25m
wire   [31:0]  araddr_cpu_mst_axi4;
wire   [31:0]  araddr_dma_axi4_cpu_s;
wire   [31:0]  araddr_vgalcd_mst_axi4;
wire   [1:0]   arburst_cpu_mst_axi4;
wire   [1:0]   arburst_dma_axi4_cpu_s;
wire   [1:0]   arburst_vgalcd_mst_axi4;
wire   [3:0]   arcache_cpu_mst_axi4;
wire   [3:0]   arcache_dma_axi4_cpu_s;
wire   [3:0]   arcache_vgalcd_mst_axi4;
wire   [2:0]   arid_cpu_mst_axi4;
wire   [3:0]   arid_dma_axi4_cpu_s;
wire   [2:0]   arid_vgalcd_mst_axi4;
wire   [7:0]   arlen_cpu_mst_axi4;
wire   [7:0]   arlen_dma_axi4_cpu_s;
wire   [7:0]   arlen_vgalcd_mst_axi4;
wire           arlock_cpu_mst_axi4;
wire           arlock_dma_axi4_cpu_s;
wire           arlock_vgalcd_mst_axi4;
wire   [2:0]   arprot_cpu_mst_axi4;
wire   [2:0]   arprot_dma_axi4_cpu_s;
wire   [2:0]   arprot_vgalcd_mst_axi4;
wire           arready_chiplink_slv_axi4_tpv;
wire           arready_dma_axi4_cpu_m;
wire           arready_psram_slv_axi4;
wire           arready_sdram_slv_axi4;
wire           arready_sram_slv_axi4;
wire   [2:0]   arsize_cpu_mst_axi4;
wire   [2:0]   arsize_dma_axi4_cpu_s;
wire   [2:0]   arsize_vgalcd_mst_axi4;
wire           arvalid_cpu_mst_axi4;
wire           arvalid_dma_axi4_cpu_s;
wire           arvalid_vgalcd_mst_axi4;
wire   [31:0]  awaddr_cpu_mst_axi4;
wire   [31:0]  awaddr_dma_axi4_cpu_s;
wire   [31:0]  awaddr_vgalcd_mst_axi4;
wire   [1:0]   awburst_cpu_mst_axi4;
wire   [1:0]   awburst_dma_axi4_cpu_s;
wire   [1:0]   awburst_vgalcd_mst_axi4;
wire   [3:0]   awcache_cpu_mst_axi4;
wire   [3:0]   awcache_dma_axi4_cpu_s;
wire   [3:0]   awcache_vgalcd_mst_axi4;
wire   [2:0]   awid_cpu_mst_axi4;
wire   [3:0]   awid_dma_axi4_cpu_s;
wire   [2:0]   awid_vgalcd_mst_axi4;
wire   [7:0]   awlen_cpu_mst_axi4;
wire   [7:0]   awlen_dma_axi4_cpu_s;
wire   [7:0]   awlen_vgalcd_mst_axi4;
wire           awlock_cpu_mst_axi4;
wire           awlock_dma_axi4_cpu_s;
wire           awlock_vgalcd_mst_axi4;
wire   [2:0]   awprot_cpu_mst_axi4;
wire   [2:0]   awprot_dma_axi4_cpu_s;
wire   [2:0]   awprot_vgalcd_mst_axi4;
wire           awready_chiplink_slv_axi4_tpv;
wire           awready_dma_axi4_cpu_m;
wire           awready_psram_slv_axi4;
wire           awready_sdram_slv_axi4;
wire           awready_sram_slv_axi4;
wire   [2:0]   awsize_cpu_mst_axi4;
wire   [2:0]   awsize_dma_axi4_cpu_s;
wire   [2:0]   awsize_vgalcd_mst_axi4;
wire           awvalid_cpu_mst_axi4;
wire           awvalid_dma_axi4_cpu_s;
wire           awvalid_vgalcd_mst_axi4;
wire   [3:0]   bid_chiplink_slv_axi4_tpv;
wire   [3:0]   bid_dma_axi4_cpu_m;
wire   [3:0]   bid_psram_slv_axi4;
wire   [3:0]   bid_sdram_slv_axi4;
wire   [3:0]   bid_sram_slv_axi4;
wire           bready_cpu_mst_axi4;
wire           bready_dma_axi4_cpu_s;
wire           bready_vgalcd_mst_axi4;
wire   [1:0]   bresp_chiplink_slv_axi4_tpv;
wire   [1:0]   bresp_dma_axi4_cpu_m;
wire   [1:0]   bresp_psram_slv_axi4;
wire   [1:0]   bresp_sdram_slv_axi4;
wire   [1:0]   bresp_sram_slv_axi4;
wire           bvalid_chiplink_slv_axi4_tpv;
wire           bvalid_dma_axi4_cpu_m;
wire           bvalid_psram_slv_axi4;
wire           bvalid_sdram_slv_axi4;
wire           bvalid_sram_slv_axi4;
wire           clk_aud_12288kclk;
wire           clk_aud_12288kclken;
wire           clk_aud_12288kresetn;
wire           clk_core_200_800mclk;
wire           clk_core_200_800mresetn;
wire           clk_peri_100mclk;
wire           clk_peri_100mclken;
wire           clk_peri_100mresetn;
wire           clk_peri_25mclk;
wire           clk_peri_25mclken;
wire           clk_peri_25mresetn;
wire   [31:0]  prdata_archinfo_slv_apb4;
wire   [31:0]  prdata_clint_slv_apb4;
wire   [31:0]  prdata_crc_slv_apb4;
wire   [31:0]  prdata_gpio_slv_apb4;
wire   [31:0]  prdata_i2c_slv_apb4;
wire   [31:0]  prdata_i2s_slv_apb4;
wire   [31:0]  prdata_plic_slv_apb4;
wire   [31:0]  prdata_ps2_slv_apb4;
wire   [31:0]  prdata_psram_slv_apb4;
wire   [31:0]  prdata_pwm0_slv_apb4;
wire   [31:0]  prdata_pwm1_slv_apb4;
wire   [31:0]  prdata_pwm2_slv_apb4;
wire   [31:0]  prdata_qspi_slv_apb4;
wire   [31:0]  prdata_rcu_slv_apb4;
wire   [31:0]  prdata_rng_slv_apb4;
wire   [31:0]  prdata_rtc_slv_apb4;
wire   [31:0]  prdata_spfs_slv_apb4_tpv;
wire   [31:0]  prdata_spi0_slv_apb4;
wire   [31:0]  prdata_spi1_slv_apb4;
wire   [31:0]  prdata_tim0_slv_apb4;
wire   [31:0]  prdata_tim1_slv_apb4;
wire   [31:0]  prdata_tim2_slv_apb4;
wire   [31:0]  prdata_tim3_slv_apb4;
wire   [31:0]  prdata_uart_slv_apb4;
wire   [31:0]  prdata_uart_slv_apb4_tpv;
wire   [31:0]  prdata_vgalcd_slv_apb4;
wire   [31:0]  prdata_wdg_slv_apb4;
wire           pready_archinfo_slv_apb4;
wire           pready_clint_slv_apb4;
wire           pready_crc_slv_apb4;
wire           pready_gpio_slv_apb4;
wire           pready_i2c_slv_apb4;
wire           pready_i2s_slv_apb4;
wire           pready_plic_slv_apb4;
wire           pready_ps2_slv_apb4;
wire           pready_psram_slv_apb4;
wire           pready_pwm0_slv_apb4;
wire           pready_pwm1_slv_apb4;
wire           pready_pwm2_slv_apb4;
wire           pready_qspi_slv_apb4;
wire           pready_rcu_slv_apb4;
wire           pready_rng_slv_apb4;
wire           pready_rtc_slv_apb4;
wire           pready_spfs_slv_apb4_tpv;
wire           pready_spi0_slv_apb4;
wire           pready_spi1_slv_apb4;
wire           pready_tim0_slv_apb4;
wire           pready_tim1_slv_apb4;
wire           pready_tim2_slv_apb4;
wire           pready_tim3_slv_apb4;
wire           pready_uart_slv_apb4;
wire           pready_uart_slv_apb4_tpv;
wire           pready_vgalcd_slv_apb4;
wire           pready_wdg_slv_apb4;
wire           pslverr_archinfo_slv_apb4;
wire           pslverr_clint_slv_apb4;
wire           pslverr_crc_slv_apb4;
wire           pslverr_gpio_slv_apb4;
wire           pslverr_i2c_slv_apb4;
wire           pslverr_i2s_slv_apb4;
wire           pslverr_plic_slv_apb4;
wire           pslverr_ps2_slv_apb4;
wire           pslverr_psram_slv_apb4;
wire           pslverr_pwm0_slv_apb4;
wire           pslverr_pwm1_slv_apb4;
wire           pslverr_pwm2_slv_apb4;
wire           pslverr_qspi_slv_apb4;
wire           pslverr_rcu_slv_apb4;
wire           pslverr_rng_slv_apb4;
wire           pslverr_rtc_slv_apb4;
wire           pslverr_spfs_slv_apb4_tpv;
wire           pslverr_spi0_slv_apb4;
wire           pslverr_spi1_slv_apb4;
wire           pslverr_tim0_slv_apb4;
wire           pslverr_tim1_slv_apb4;
wire           pslverr_tim2_slv_apb4;
wire           pslverr_tim3_slv_apb4;
wire           pslverr_uart_slv_apb4;
wire           pslverr_uart_slv_apb4_tpv;
wire           pslverr_vgalcd_slv_apb4;
wire           pslverr_wdg_slv_apb4;
wire   [63:0]  rdata_chiplink_slv_axi4_tpv;
wire   [31:0]  rdata_dma_axi4_cpu_m;
wire   [63:0]  rdata_psram_slv_axi4;
wire   [31:0]  rdata_sdram_slv_axi4;
wire   [63:0]  rdata_sram_slv_axi4;
wire   [3:0]   rid_chiplink_slv_axi4_tpv;
wire   [3:0]   rid_dma_axi4_cpu_m;
wire   [3:0]   rid_psram_slv_axi4;
wire   [3:0]   rid_sdram_slv_axi4;
wire   [3:0]   rid_sram_slv_axi4;
wire           rlast_chiplink_slv_axi4_tpv;
wire           rlast_dma_axi4_cpu_m;
wire           rlast_psram_slv_axi4;
wire           rlast_sdram_slv_axi4;
wire           rlast_sram_slv_axi4;
wire           rready_cpu_mst_axi4;
wire           rready_dma_axi4_cpu_s;
wire           rready_vgalcd_mst_axi4;
wire   [1:0]   rresp_chiplink_slv_axi4_tpv;
wire   [1:0]   rresp_dma_axi4_cpu_m;
wire   [1:0]   rresp_psram_slv_axi4;
wire   [1:0]   rresp_sdram_slv_axi4;
wire   [1:0]   rresp_sram_slv_axi4;
wire           rvalid_chiplink_slv_axi4_tpv;
wire           rvalid_dma_axi4_cpu_m;
wire           rvalid_psram_slv_axi4;
wire           rvalid_sdram_slv_axi4;
wire           rvalid_sram_slv_axi4;
wire   [31:0]  wdata_cpu_mst_axi4;
wire   [63:0]  wdata_dma_axi4_cpu_s;
wire   [63:0]  wdata_vgalcd_mst_axi4;
wire           wlast_cpu_mst_axi4;
wire           wlast_dma_axi4_cpu_s;
wire           wlast_vgalcd_mst_axi4;
wire           wready_chiplink_slv_axi4_tpv;
wire           wready_dma_axi4_cpu_m;
wire           wready_psram_slv_axi4;
wire           wready_sdram_slv_axi4;
wire           wready_sram_slv_axi4;
wire   [3:0]   wstrb_cpu_mst_axi4;
wire   [7:0]   wstrb_dma_axi4_cpu_s;
wire   [7:0]   wstrb_vgalcd_mst_axi4;
wire           wvalid_cpu_mst_axi4;
wire           wvalid_dma_axi4_cpu_s;
wire           wvalid_vgalcd_mst_axi4;



//-----------------------------------------------------------------------------
// Sub-Modules Instantiation
//-----------------------------------------------------------------------------

nic400_cd_clk_aud_12288k_ysyx_rv32     u_cd_clk_aud_12288k (
  .clk_aud_12288kclk    (clk_aud_12288kclk),    // i2s_slv_apb4
  .clk_aud_12288kresetn (clk_aud_12288kresetn),    // i2s_slv_apb4
  .paddr_i2s_slv_apb4   (paddr_i2s_slv_apb4),    // i2s_slv_apb4
  .pselx_i2s_slv_apb4   (pselx_i2s_slv_apb4),    // i2s_slv_apb4
  .penable_i2s_slv_apb4 (penable_i2s_slv_apb4),    // i2s_slv_apb4
  .pwrite_i2s_slv_apb4  (pwrite_i2s_slv_apb4),    // i2s_slv_apb4
  .prdata_i2s_slv_apb4  (prdata_i2s_slv_apb4),    // i2s_slv_apb4
  .pwdata_i2s_slv_apb4  (pwdata_i2s_slv_apb4),    // i2s_slv_apb4
  .pprot_i2s_slv_apb4   (pprot_i2s_slv_apb4),    // i2s_slv_apb4
  .pstrb_i2s_slv_apb4   (pstrb_i2s_slv_apb4),    // i2s_slv_apb4
  .pready_i2s_slv_apb4  (pready_i2s_slv_apb4),    // i2s_slv_apb4
  .pslverr_i2s_slv_apb4 (pslverr_i2s_slv_apb4),    // i2s_slv_apb4
  .clk_aud_12288kclken  (clk_aud_12288kclken),    // i2s_slv_apb4
  .pack_i2s_slv_apb4_int_master_async (pack_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_master_async
  .preq_i2s_slv_apb4_int_master_async (preq_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_master_async
  .pfwdpayld_i2s_slv_apb4_int_master_async (pfwdpayld_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_master_async
  .prevpayld_i2s_slv_apb4_int_master_async (prevpayld_tpv_gp_apb4_i2s_slv_apb4_int_async)    // i2s_slv_apb4_int_master_async
);


nic400_cd_clk_core_200_800m_ysyx_rv32     u_cd_clk_core_200_800m (
  .aw_data_chiplink_slv_axi4_tpv_ib_int_async (aw_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_data_chiplink_slv_axi4_tpv_ib_int_async (ar_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_data_chiplink_slv_axi4_tpv_ib_int_async (w_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_data_chiplink_slv_axi4_tpv_ib_int_async (r_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_data_chiplink_slv_axi4_tpv_ib_int_async (b_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .awid_cpu_mst_axi4    (awid_cpu_mst_axi4),    // cpu_mst_axi4
  .awaddr_cpu_mst_axi4  (awaddr_cpu_mst_axi4),    // cpu_mst_axi4
  .awlen_cpu_mst_axi4   (awlen_cpu_mst_axi4),    // cpu_mst_axi4
  .awsize_cpu_mst_axi4  (awsize_cpu_mst_axi4),    // cpu_mst_axi4
  .awburst_cpu_mst_axi4 (awburst_cpu_mst_axi4),    // cpu_mst_axi4
  .awlock_cpu_mst_axi4  (awlock_cpu_mst_axi4),    // cpu_mst_axi4
  .awcache_cpu_mst_axi4 (awcache_cpu_mst_axi4),    // cpu_mst_axi4
  .awprot_cpu_mst_axi4  (awprot_cpu_mst_axi4),    // cpu_mst_axi4
  .awvalid_cpu_mst_axi4 (awvalid_cpu_mst_axi4),    // cpu_mst_axi4
  .awready_cpu_mst_axi4 (awready_cpu_mst_axi4),    // cpu_mst_axi4
  .wdata_cpu_mst_axi4   (wdata_cpu_mst_axi4),    // cpu_mst_axi4
  .wstrb_cpu_mst_axi4   (wstrb_cpu_mst_axi4),    // cpu_mst_axi4
  .wlast_cpu_mst_axi4   (wlast_cpu_mst_axi4),    // cpu_mst_axi4
  .wvalid_cpu_mst_axi4  (wvalid_cpu_mst_axi4),    // cpu_mst_axi4
  .wready_cpu_mst_axi4  (wready_cpu_mst_axi4),    // cpu_mst_axi4
  .bid_cpu_mst_axi4     (bid_cpu_mst_axi4),    // cpu_mst_axi4
  .bresp_cpu_mst_axi4   (bresp_cpu_mst_axi4),    // cpu_mst_axi4
  .bvalid_cpu_mst_axi4  (bvalid_cpu_mst_axi4),    // cpu_mst_axi4
  .bready_cpu_mst_axi4  (bready_cpu_mst_axi4),    // cpu_mst_axi4
  .arid_cpu_mst_axi4    (arid_cpu_mst_axi4),    // cpu_mst_axi4
  .araddr_cpu_mst_axi4  (araddr_cpu_mst_axi4),    // cpu_mst_axi4
  .arlen_cpu_mst_axi4   (arlen_cpu_mst_axi4),    // cpu_mst_axi4
  .arsize_cpu_mst_axi4  (arsize_cpu_mst_axi4),    // cpu_mst_axi4
  .arburst_cpu_mst_axi4 (arburst_cpu_mst_axi4),    // cpu_mst_axi4
  .arlock_cpu_mst_axi4  (arlock_cpu_mst_axi4),    // cpu_mst_axi4
  .arcache_cpu_mst_axi4 (arcache_cpu_mst_axi4),    // cpu_mst_axi4
  .arprot_cpu_mst_axi4  (arprot_cpu_mst_axi4),    // cpu_mst_axi4
  .arvalid_cpu_mst_axi4 (arvalid_cpu_mst_axi4),    // cpu_mst_axi4
  .arready_cpu_mst_axi4 (arready_cpu_mst_axi4),    // cpu_mst_axi4
  .rid_cpu_mst_axi4     (rid_cpu_mst_axi4),    // cpu_mst_axi4
  .rdata_cpu_mst_axi4   (rdata_cpu_mst_axi4),    // cpu_mst_axi4
  .rresp_cpu_mst_axi4   (rresp_cpu_mst_axi4),    // cpu_mst_axi4
  .rlast_cpu_mst_axi4   (rlast_cpu_mst_axi4),    // cpu_mst_axi4
  .rvalid_cpu_mst_axi4  (rvalid_cpu_mst_axi4),    // cpu_mst_axi4
  .rready_cpu_mst_axi4  (rready_cpu_mst_axi4),    // cpu_mst_axi4
  .aw_data_dma_axi4_cpu_ib_int_async (aw_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .aw_wpntr_gry_dma_axi4_cpu_ib_int_async (aw_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .aw_rpntr_bin_dma_axi4_cpu_ib_int_async (aw_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .aw_rpntr_gry_dma_axi4_cpu_ib_int_async (aw_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_data_dma_axi4_cpu_ib_int_async (ar_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_wpntr_gry_dma_axi4_cpu_ib_int_async (ar_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_rpntr_bin_dma_axi4_cpu_ib_int_async (ar_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_rpntr_gry_dma_axi4_cpu_ib_int_async (ar_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_data_dma_axi4_cpu_ib_int_async (w_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_wpntr_gry_dma_axi4_cpu_ib_int_async (w_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_rpntr_bin_dma_axi4_cpu_ib_int_async (w_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_rpntr_gry_dma_axi4_cpu_ib_int_async (w_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_data_dma_axi4_cpu_ib_int_async (r_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_wpntr_gry_dma_axi4_cpu_ib_int_async (r_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_rpntr_bin_dma_axi4_cpu_ib_int_async (r_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_rpntr_gry_dma_axi4_cpu_ib_int_async (r_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_data_dma_axi4_cpu_ib_int_async (b_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_wpntr_gry_dma_axi4_cpu_ib_int_async (b_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_rpntr_bin_dma_axi4_cpu_ib_int_async (b_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_rpntr_gry_dma_axi4_cpu_ib_int_async (b_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .awid_dma_axi4_cpu_m  (awid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awaddr_dma_axi4_cpu_m (awaddr_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awlen_dma_axi4_cpu_m (awlen_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awsize_dma_axi4_cpu_m (awsize_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awburst_dma_axi4_cpu_m (awburst_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awlock_dma_axi4_cpu_m (awlock_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awcache_dma_axi4_cpu_m (awcache_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awprot_dma_axi4_cpu_m (awprot_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awvalid_dma_axi4_cpu_m (awvalid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .awready_dma_axi4_cpu_m (awready_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .wdata_dma_axi4_cpu_m (wdata_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .wstrb_dma_axi4_cpu_m (wstrb_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .wlast_dma_axi4_cpu_m (wlast_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .wvalid_dma_axi4_cpu_m (wvalid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .wready_dma_axi4_cpu_m (wready_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .bid_dma_axi4_cpu_m   (bid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .bresp_dma_axi4_cpu_m (bresp_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .bvalid_dma_axi4_cpu_m (bvalid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .bready_dma_axi4_cpu_m (bready_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arid_dma_axi4_cpu_m  (arid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .araddr_dma_axi4_cpu_m (araddr_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arlen_dma_axi4_cpu_m (arlen_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arsize_dma_axi4_cpu_m (arsize_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arburst_dma_axi4_cpu_m (arburst_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arlock_dma_axi4_cpu_m (arlock_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arcache_dma_axi4_cpu_m (arcache_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arprot_dma_axi4_cpu_m (arprot_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arvalid_dma_axi4_cpu_m (arvalid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .arready_dma_axi4_cpu_m (arready_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .rid_dma_axi4_cpu_m   (rid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .rdata_dma_axi4_cpu_m (rdata_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .rresp_dma_axi4_cpu_m (rresp_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .rlast_dma_axi4_cpu_m (rlast_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .rvalid_dma_axi4_cpu_m (rvalid_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .rready_dma_axi4_cpu_m (rready_dma_axi4_cpu_m),    // dma_axi4_cpu_m
  .a_data_perip0_gp_apb4_ib_int_async (a_data_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_wpntr_gry_perip0_gp_apb4_ib_int_async (a_wpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_rpntr_bin_perip0_gp_apb4_ib_int_async (a_rpntr_bin_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_rpntr_gry_perip0_gp_apb4_ib_int_async (a_rpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_data_perip0_gp_apb4_ib_int_async (w_data_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_wpntr_gry_perip0_gp_apb4_ib_int_async (w_wpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_rpntr_bin_perip0_gp_apb4_ib_int_async (w_rpntr_bin_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_rpntr_gry_perip0_gp_apb4_ib_int_async (w_rpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_data_perip0_gp_apb4_ib_int_async (d_data_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_wpntr_gry_perip0_gp_apb4_ib_int_async (d_wpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_rpntr_bin_perip0_gp_apb4_ib_int_async (d_rpntr_bin_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_rpntr_gry_perip0_gp_apb4_ib_int_async (d_rpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_data_perip1_gp_apb4_ib_int_async (a_data_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .a_wpntr_gry_perip1_gp_apb4_ib_int_async (a_wpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .a_rpntr_bin_perip1_gp_apb4_ib_int_async (a_rpntr_bin_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .a_rpntr_gry_perip1_gp_apb4_ib_int_async (a_rpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_data_perip1_gp_apb4_ib_int_async (w_data_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_wpntr_gry_perip1_gp_apb4_ib_int_async (w_wpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_rpntr_bin_perip1_gp_apb4_ib_int_async (w_rpntr_bin_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_rpntr_gry_perip1_gp_apb4_ib_int_async (w_rpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_data_perip1_gp_apb4_ib_int_async (d_data_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_wpntr_gry_perip1_gp_apb4_ib_int_async (d_wpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_rpntr_bin_perip1_gp_apb4_ib_int_async (d_rpntr_bin_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_rpntr_gry_perip1_gp_apb4_ib_int_async (d_rpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .aw_data_psram_slv_axi4_ib_int_async (aw_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_wpntr_gry_psram_slv_axi4_ib_int_async (aw_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_rpntr_bin_psram_slv_axi4_ib_int_async (aw_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_rpntr_gry_psram_slv_axi4_ib_int_async (aw_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_data_psram_slv_axi4_ib_int_async (ar_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_wpntr_gry_psram_slv_axi4_ib_int_async (ar_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_rpntr_bin_psram_slv_axi4_ib_int_async (ar_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_rpntr_gry_psram_slv_axi4_ib_int_async (ar_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_data_psram_slv_axi4_ib_int_async (w_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_wpntr_gry_psram_slv_axi4_ib_int_async (w_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_rpntr_bin_psram_slv_axi4_ib_int_async (w_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_rpntr_gry_psram_slv_axi4_ib_int_async (w_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_data_psram_slv_axi4_ib_int_async (r_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_wpntr_gry_psram_slv_axi4_ib_int_async (r_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_rpntr_bin_psram_slv_axi4_ib_int_async (r_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_rpntr_gry_psram_slv_axi4_ib_int_async (r_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_data_psram_slv_axi4_ib_int_async (b_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_wpntr_gry_psram_slv_axi4_ib_int_async (b_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_rpntr_bin_psram_slv_axi4_ib_int_async (b_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_rpntr_gry_psram_slv_axi4_ib_int_async (b_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_data_sdram_slv_axi4_ib_int_async (aw_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .aw_wpntr_gry_sdram_slv_axi4_ib_int_async (aw_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .aw_rpntr_bin_sdram_slv_axi4_ib_int_async (aw_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .aw_rpntr_gry_sdram_slv_axi4_ib_int_async (aw_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_data_sdram_slv_axi4_ib_int_async (ar_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_wpntr_gry_sdram_slv_axi4_ib_int_async (ar_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_rpntr_bin_sdram_slv_axi4_ib_int_async (ar_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_rpntr_gry_sdram_slv_axi4_ib_int_async (ar_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_data_sdram_slv_axi4_ib_int_async (w_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_wpntr_gry_sdram_slv_axi4_ib_int_async (w_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_rpntr_bin_sdram_slv_axi4_ib_int_async (w_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_rpntr_gry_sdram_slv_axi4_ib_int_async (w_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_data_sdram_slv_axi4_ib_int_async (r_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_wpntr_gry_sdram_slv_axi4_ib_int_async (r_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_rpntr_bin_sdram_slv_axi4_ib_int_async (r_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_rpntr_gry_sdram_slv_axi4_ib_int_async (r_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_data_sdram_slv_axi4_ib_int_async (b_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_wpntr_gry_sdram_slv_axi4_ib_int_async (b_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_rpntr_bin_sdram_slv_axi4_ib_int_async (b_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_rpntr_gry_sdram_slv_axi4_ib_int_async (b_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .clk_core_200_800mclk (clk_core_200_800mclk),    // sram_slv_axi4
  .clk_core_200_800mresetn (clk_core_200_800mresetn),    // sram_slv_axi4
  .awid_sram_slv_axi4   (awid_sram_slv_axi4),    // sram_slv_axi4
  .awaddr_sram_slv_axi4 (awaddr_sram_slv_axi4),    // sram_slv_axi4
  .awlen_sram_slv_axi4  (awlen_sram_slv_axi4),    // sram_slv_axi4
  .awsize_sram_slv_axi4 (awsize_sram_slv_axi4),    // sram_slv_axi4
  .awburst_sram_slv_axi4 (awburst_sram_slv_axi4),    // sram_slv_axi4
  .awlock_sram_slv_axi4 (awlock_sram_slv_axi4),    // sram_slv_axi4
  .awcache_sram_slv_axi4 (awcache_sram_slv_axi4),    // sram_slv_axi4
  .awprot_sram_slv_axi4 (awprot_sram_slv_axi4),    // sram_slv_axi4
  .awvalid_sram_slv_axi4 (awvalid_sram_slv_axi4),    // sram_slv_axi4
  .awready_sram_slv_axi4 (awready_sram_slv_axi4),    // sram_slv_axi4
  .wdata_sram_slv_axi4  (wdata_sram_slv_axi4),    // sram_slv_axi4
  .wstrb_sram_slv_axi4  (wstrb_sram_slv_axi4),    // sram_slv_axi4
  .wlast_sram_slv_axi4  (wlast_sram_slv_axi4),    // sram_slv_axi4
  .wvalid_sram_slv_axi4 (wvalid_sram_slv_axi4),    // sram_slv_axi4
  .wready_sram_slv_axi4 (wready_sram_slv_axi4),    // sram_slv_axi4
  .bid_sram_slv_axi4    (bid_sram_slv_axi4),    // sram_slv_axi4
  .bresp_sram_slv_axi4  (bresp_sram_slv_axi4),    // sram_slv_axi4
  .bvalid_sram_slv_axi4 (bvalid_sram_slv_axi4),    // sram_slv_axi4
  .bready_sram_slv_axi4 (bready_sram_slv_axi4),    // sram_slv_axi4
  .arid_sram_slv_axi4   (arid_sram_slv_axi4),    // sram_slv_axi4
  .araddr_sram_slv_axi4 (araddr_sram_slv_axi4),    // sram_slv_axi4
  .arlen_sram_slv_axi4  (arlen_sram_slv_axi4),    // sram_slv_axi4
  .arsize_sram_slv_axi4 (arsize_sram_slv_axi4),    // sram_slv_axi4
  .arburst_sram_slv_axi4 (arburst_sram_slv_axi4),    // sram_slv_axi4
  .arlock_sram_slv_axi4 (arlock_sram_slv_axi4),    // sram_slv_axi4
  .arcache_sram_slv_axi4 (arcache_sram_slv_axi4),    // sram_slv_axi4
  .arprot_sram_slv_axi4 (arprot_sram_slv_axi4),    // sram_slv_axi4
  .arvalid_sram_slv_axi4 (arvalid_sram_slv_axi4),    // sram_slv_axi4
  .arready_sram_slv_axi4 (arready_sram_slv_axi4),    // sram_slv_axi4
  .rid_sram_slv_axi4    (rid_sram_slv_axi4),    // sram_slv_axi4
  .rdata_sram_slv_axi4  (rdata_sram_slv_axi4),    // sram_slv_axi4
  .rresp_sram_slv_axi4  (rresp_sram_slv_axi4),    // sram_slv_axi4
  .rlast_sram_slv_axi4  (rlast_sram_slv_axi4),    // sram_slv_axi4
  .rvalid_sram_slv_axi4 (rvalid_sram_slv_axi4),    // sram_slv_axi4
  .rready_sram_slv_axi4 (rready_sram_slv_axi4),    // sram_slv_axi4
  .a_data_sys_gp_apb4_ib_int_async (a_data_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_wpntr_gry_sys_gp_apb4_ib_int_async (a_wpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_rpntr_bin_sys_gp_apb4_ib_int_async (a_rpntr_bin_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_rpntr_gry_sys_gp_apb4_ib_int_async (a_rpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_data_sys_gp_apb4_ib_int_async (w_data_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_wpntr_gry_sys_gp_apb4_ib_int_async (w_wpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_rpntr_bin_sys_gp_apb4_ib_int_async (w_rpntr_bin_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_rpntr_gry_sys_gp_apb4_ib_int_async (w_rpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_data_sys_gp_apb4_ib_int_async (d_data_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_wpntr_gry_sys_gp_apb4_ib_int_async (d_wpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_rpntr_bin_sys_gp_apb4_ib_int_async (d_rpntr_bin_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_rpntr_gry_sys_gp_apb4_ib_int_async (d_rpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_data_tpv_gp_apb4_ib_int_async (a_data_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .a_wpntr_gry_tpv_gp_apb4_ib_int_async (a_wpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .a_rpntr_bin_tpv_gp_apb4_ib_int_async (a_rpntr_bin_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .a_rpntr_gry_tpv_gp_apb4_ib_int_async (a_rpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_data_tpv_gp_apb4_ib_int_async (w_data_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_wpntr_gry_tpv_gp_apb4_ib_int_async (w_wpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_rpntr_bin_tpv_gp_apb4_ib_int_async (w_rpntr_bin_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_rpntr_gry_tpv_gp_apb4_ib_int_async (w_rpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_data_tpv_gp_apb4_ib_int_async (d_data_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_wpntr_gry_tpv_gp_apb4_ib_int_async (d_wpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_rpntr_bin_tpv_gp_apb4_ib_int_async (d_rpntr_bin_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_rpntr_gry_tpv_gp_apb4_ib_int_async (d_rpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .aw_data_vgalcd_mst_axi4_ib_int_async (aw_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async (aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async (aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async (aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_data_vgalcd_mst_axi4_ib_int_async (ar_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async (ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async (ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async (ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_data_vgalcd_mst_axi4_ib_int_async (w_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_wpntr_gry_vgalcd_mst_axi4_ib_int_async (w_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_rpntr_bin_vgalcd_mst_axi4_ib_int_async (w_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_rpntr_gry_vgalcd_mst_axi4_ib_int_async (w_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_data_vgalcd_mst_axi4_ib_int_async (r_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_wpntr_gry_vgalcd_mst_axi4_ib_int_async (r_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_rpntr_bin_vgalcd_mst_axi4_ib_int_async (r_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_rpntr_gry_vgalcd_mst_axi4_ib_int_async (r_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_data_vgalcd_mst_axi4_ib_int_async (b_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_wpntr_gry_vgalcd_mst_axi4_ib_int_async (b_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_rpntr_bin_vgalcd_mst_axi4_ib_int_async (b_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_rpntr_gry_vgalcd_mst_axi4_ib_int_async (b_rpntr_gry_vgalcd_mst_axi4_ib_int_async)    // vgalcd_mst_axi4_ib_int_async
);


nic400_cd_clk_peri_100m_ysyx_rv32     u_cd_clk_peri_100m (
  .paddr_archinfo_slv_apb4 (paddr_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pselx_archinfo_slv_apb4 (pselx_archinfo_slv_apb4),    // archinfo_slv_apb4
  .penable_archinfo_slv_apb4 (penable_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pwrite_archinfo_slv_apb4 (pwrite_archinfo_slv_apb4),    // archinfo_slv_apb4
  .prdata_archinfo_slv_apb4 (prdata_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pwdata_archinfo_slv_apb4 (pwdata_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pprot_archinfo_slv_apb4 (pprot_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pstrb_archinfo_slv_apb4 (pstrb_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pready_archinfo_slv_apb4 (pready_archinfo_slv_apb4),    // archinfo_slv_apb4
  .pslverr_archinfo_slv_apb4 (pslverr_archinfo_slv_apb4),    // archinfo_slv_apb4
  .paddr_clint_slv_apb4 (paddr_clint_slv_apb4),    // clint_slv_apb4
  .pselx_clint_slv_apb4 (pselx_clint_slv_apb4),    // clint_slv_apb4
  .penable_clint_slv_apb4 (penable_clint_slv_apb4),    // clint_slv_apb4
  .pwrite_clint_slv_apb4 (pwrite_clint_slv_apb4),    // clint_slv_apb4
  .prdata_clint_slv_apb4 (prdata_clint_slv_apb4),    // clint_slv_apb4
  .pwdata_clint_slv_apb4 (pwdata_clint_slv_apb4),    // clint_slv_apb4
  .pprot_clint_slv_apb4 (pprot_clint_slv_apb4),    // clint_slv_apb4
  .pstrb_clint_slv_apb4 (pstrb_clint_slv_apb4),    // clint_slv_apb4
  .pready_clint_slv_apb4 (pready_clint_slv_apb4),    // clint_slv_apb4
  .pslverr_clint_slv_apb4 (pslverr_clint_slv_apb4),    // clint_slv_apb4
  .paddr_crc_slv_apb4   (paddr_crc_slv_apb4),    // crc_slv_apb4
  .pselx_crc_slv_apb4   (pselx_crc_slv_apb4),    // crc_slv_apb4
  .penable_crc_slv_apb4 (penable_crc_slv_apb4),    // crc_slv_apb4
  .pwrite_crc_slv_apb4  (pwrite_crc_slv_apb4),    // crc_slv_apb4
  .prdata_crc_slv_apb4  (prdata_crc_slv_apb4),    // crc_slv_apb4
  .pwdata_crc_slv_apb4  (pwdata_crc_slv_apb4),    // crc_slv_apb4
  .pprot_crc_slv_apb4   (pprot_crc_slv_apb4),    // crc_slv_apb4
  .pstrb_crc_slv_apb4   (pstrb_crc_slv_apb4),    // crc_slv_apb4
  .pready_crc_slv_apb4  (pready_crc_slv_apb4),    // crc_slv_apb4
  .pslverr_crc_slv_apb4 (pslverr_crc_slv_apb4),    // crc_slv_apb4
  .paddr_gpio_slv_apb4  (paddr_gpio_slv_apb4),    // gpio_slv_apb4
  .pselx_gpio_slv_apb4  (pselx_gpio_slv_apb4),    // gpio_slv_apb4
  .penable_gpio_slv_apb4 (penable_gpio_slv_apb4),    // gpio_slv_apb4
  .pwrite_gpio_slv_apb4 (pwrite_gpio_slv_apb4),    // gpio_slv_apb4
  .prdata_gpio_slv_apb4 (prdata_gpio_slv_apb4),    // gpio_slv_apb4
  .pwdata_gpio_slv_apb4 (pwdata_gpio_slv_apb4),    // gpio_slv_apb4
  .pprot_gpio_slv_apb4  (pprot_gpio_slv_apb4),    // gpio_slv_apb4
  .pstrb_gpio_slv_apb4  (pstrb_gpio_slv_apb4),    // gpio_slv_apb4
  .pready_gpio_slv_apb4 (pready_gpio_slv_apb4),    // gpio_slv_apb4
  .pslverr_gpio_slv_apb4 (pslverr_gpio_slv_apb4),    // gpio_slv_apb4
  .paddr_i2c_slv_apb4   (paddr_i2c_slv_apb4),    // i2c_slv_apb4
  .pselx_i2c_slv_apb4   (pselx_i2c_slv_apb4),    // i2c_slv_apb4
  .penable_i2c_slv_apb4 (penable_i2c_slv_apb4),    // i2c_slv_apb4
  .pwrite_i2c_slv_apb4  (pwrite_i2c_slv_apb4),    // i2c_slv_apb4
  .prdata_i2c_slv_apb4  (prdata_i2c_slv_apb4),    // i2c_slv_apb4
  .pwdata_i2c_slv_apb4  (pwdata_i2c_slv_apb4),    // i2c_slv_apb4
  .pprot_i2c_slv_apb4   (pprot_i2c_slv_apb4),    // i2c_slv_apb4
  .pstrb_i2c_slv_apb4   (pstrb_i2c_slv_apb4),    // i2c_slv_apb4
  .pready_i2c_slv_apb4  (pready_i2c_slv_apb4),    // i2c_slv_apb4
  .pslverr_i2c_slv_apb4 (pslverr_i2c_slv_apb4),    // i2c_slv_apb4
  .a_data_perip0_gp_apb4_ib_int_async (a_data_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_wpntr_gry_perip0_gp_apb4_ib_int_async (a_wpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_rpntr_bin_perip0_gp_apb4_ib_int_async (a_rpntr_bin_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_rpntr_gry_perip0_gp_apb4_ib_int_async (a_rpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_data_perip0_gp_apb4_ib_int_async (w_data_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_wpntr_gry_perip0_gp_apb4_ib_int_async (w_wpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_rpntr_bin_perip0_gp_apb4_ib_int_async (w_rpntr_bin_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .w_rpntr_gry_perip0_gp_apb4_ib_int_async (w_rpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_data_perip0_gp_apb4_ib_int_async (d_data_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_wpntr_gry_perip0_gp_apb4_ib_int_async (d_wpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_rpntr_bin_perip0_gp_apb4_ib_int_async (d_rpntr_bin_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .d_rpntr_gry_perip0_gp_apb4_ib_int_async (d_rpntr_gry_perip0_gp_apb4_ib_int_async),    // perip0_gp_apb4_ib_int_async
  .a_data_perip1_gp_apb4_ib_int_async (a_data_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .a_wpntr_gry_perip1_gp_apb4_ib_int_async (a_wpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .a_rpntr_bin_perip1_gp_apb4_ib_int_async (a_rpntr_bin_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .a_rpntr_gry_perip1_gp_apb4_ib_int_async (a_rpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_data_perip1_gp_apb4_ib_int_async (w_data_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_wpntr_gry_perip1_gp_apb4_ib_int_async (w_wpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_rpntr_bin_perip1_gp_apb4_ib_int_async (w_rpntr_bin_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .w_rpntr_gry_perip1_gp_apb4_ib_int_async (w_rpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_data_perip1_gp_apb4_ib_int_async (d_data_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_wpntr_gry_perip1_gp_apb4_ib_int_async (d_wpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_rpntr_bin_perip1_gp_apb4_ib_int_async (d_rpntr_bin_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .d_rpntr_gry_perip1_gp_apb4_ib_int_async (d_rpntr_gry_perip1_gp_apb4_ib_int_async),    // perip1_gp_apb4_ib_int_async
  .paddr_plic_slv_apb4  (paddr_plic_slv_apb4),    // plic_slv_apb4
  .pselx_plic_slv_apb4  (pselx_plic_slv_apb4),    // plic_slv_apb4
  .penable_plic_slv_apb4 (penable_plic_slv_apb4),    // plic_slv_apb4
  .pwrite_plic_slv_apb4 (pwrite_plic_slv_apb4),    // plic_slv_apb4
  .prdata_plic_slv_apb4 (prdata_plic_slv_apb4),    // plic_slv_apb4
  .pwdata_plic_slv_apb4 (pwdata_plic_slv_apb4),    // plic_slv_apb4
  .pprot_plic_slv_apb4  (pprot_plic_slv_apb4),    // plic_slv_apb4
  .pstrb_plic_slv_apb4  (pstrb_plic_slv_apb4),    // plic_slv_apb4
  .pready_plic_slv_apb4 (pready_plic_slv_apb4),    // plic_slv_apb4
  .pslverr_plic_slv_apb4 (pslverr_plic_slv_apb4),    // plic_slv_apb4
  .paddr_ps2_slv_apb4   (paddr_ps2_slv_apb4),    // ps2_slv_apb4
  .pselx_ps2_slv_apb4   (pselx_ps2_slv_apb4),    // ps2_slv_apb4
  .penable_ps2_slv_apb4 (penable_ps2_slv_apb4),    // ps2_slv_apb4
  .pwrite_ps2_slv_apb4  (pwrite_ps2_slv_apb4),    // ps2_slv_apb4
  .prdata_ps2_slv_apb4  (prdata_ps2_slv_apb4),    // ps2_slv_apb4
  .pwdata_ps2_slv_apb4  (pwdata_ps2_slv_apb4),    // ps2_slv_apb4
  .pprot_ps2_slv_apb4   (pprot_ps2_slv_apb4),    // ps2_slv_apb4
  .pstrb_ps2_slv_apb4   (pstrb_ps2_slv_apb4),    // ps2_slv_apb4
  .pready_ps2_slv_apb4  (pready_ps2_slv_apb4),    // ps2_slv_apb4
  .pslverr_ps2_slv_apb4 (pslverr_ps2_slv_apb4),    // ps2_slv_apb4
  .paddr_psram_slv_apb4 (paddr_psram_slv_apb4),    // psram_slv_apb4
  .pselx_psram_slv_apb4 (pselx_psram_slv_apb4),    // psram_slv_apb4
  .penable_psram_slv_apb4 (penable_psram_slv_apb4),    // psram_slv_apb4
  .pwrite_psram_slv_apb4 (pwrite_psram_slv_apb4),    // psram_slv_apb4
  .prdata_psram_slv_apb4 (prdata_psram_slv_apb4),    // psram_slv_apb4
  .pwdata_psram_slv_apb4 (pwdata_psram_slv_apb4),    // psram_slv_apb4
  .pprot_psram_slv_apb4 (pprot_psram_slv_apb4),    // psram_slv_apb4
  .pstrb_psram_slv_apb4 (pstrb_psram_slv_apb4),    // psram_slv_apb4
  .pready_psram_slv_apb4 (pready_psram_slv_apb4),    // psram_slv_apb4
  .pslverr_psram_slv_apb4 (pslverr_psram_slv_apb4),    // psram_slv_apb4
  .awid_psram_slv_axi4  (awid_psram_slv_axi4),    // psram_slv_axi4
  .awaddr_psram_slv_axi4 (awaddr_psram_slv_axi4),    // psram_slv_axi4
  .awlen_psram_slv_axi4 (awlen_psram_slv_axi4),    // psram_slv_axi4
  .awsize_psram_slv_axi4 (awsize_psram_slv_axi4),    // psram_slv_axi4
  .awburst_psram_slv_axi4 (awburst_psram_slv_axi4),    // psram_slv_axi4
  .awlock_psram_slv_axi4 (awlock_psram_slv_axi4),    // psram_slv_axi4
  .awcache_psram_slv_axi4 (awcache_psram_slv_axi4),    // psram_slv_axi4
  .awprot_psram_slv_axi4 (awprot_psram_slv_axi4),    // psram_slv_axi4
  .awvalid_psram_slv_axi4 (awvalid_psram_slv_axi4),    // psram_slv_axi4
  .awready_psram_slv_axi4 (awready_psram_slv_axi4),    // psram_slv_axi4
  .wdata_psram_slv_axi4 (wdata_psram_slv_axi4),    // psram_slv_axi4
  .wstrb_psram_slv_axi4 (wstrb_psram_slv_axi4),    // psram_slv_axi4
  .wlast_psram_slv_axi4 (wlast_psram_slv_axi4),    // psram_slv_axi4
  .wvalid_psram_slv_axi4 (wvalid_psram_slv_axi4),    // psram_slv_axi4
  .wready_psram_slv_axi4 (wready_psram_slv_axi4),    // psram_slv_axi4
  .bid_psram_slv_axi4   (bid_psram_slv_axi4),    // psram_slv_axi4
  .bresp_psram_slv_axi4 (bresp_psram_slv_axi4),    // psram_slv_axi4
  .bvalid_psram_slv_axi4 (bvalid_psram_slv_axi4),    // psram_slv_axi4
  .bready_psram_slv_axi4 (bready_psram_slv_axi4),    // psram_slv_axi4
  .arid_psram_slv_axi4  (arid_psram_slv_axi4),    // psram_slv_axi4
  .araddr_psram_slv_axi4 (araddr_psram_slv_axi4),    // psram_slv_axi4
  .arlen_psram_slv_axi4 (arlen_psram_slv_axi4),    // psram_slv_axi4
  .arsize_psram_slv_axi4 (arsize_psram_slv_axi4),    // psram_slv_axi4
  .arburst_psram_slv_axi4 (arburst_psram_slv_axi4),    // psram_slv_axi4
  .arlock_psram_slv_axi4 (arlock_psram_slv_axi4),    // psram_slv_axi4
  .arcache_psram_slv_axi4 (arcache_psram_slv_axi4),    // psram_slv_axi4
  .arprot_psram_slv_axi4 (arprot_psram_slv_axi4),    // psram_slv_axi4
  .arvalid_psram_slv_axi4 (arvalid_psram_slv_axi4),    // psram_slv_axi4
  .arready_psram_slv_axi4 (arready_psram_slv_axi4),    // psram_slv_axi4
  .rid_psram_slv_axi4   (rid_psram_slv_axi4),    // psram_slv_axi4
  .rdata_psram_slv_axi4 (rdata_psram_slv_axi4),    // psram_slv_axi4
  .rresp_psram_slv_axi4 (rresp_psram_slv_axi4),    // psram_slv_axi4
  .rlast_psram_slv_axi4 (rlast_psram_slv_axi4),    // psram_slv_axi4
  .rvalid_psram_slv_axi4 (rvalid_psram_slv_axi4),    // psram_slv_axi4
  .rready_psram_slv_axi4 (rready_psram_slv_axi4),    // psram_slv_axi4
  .aw_data_psram_slv_axi4_ib_int_async (aw_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_wpntr_gry_psram_slv_axi4_ib_int_async (aw_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_rpntr_bin_psram_slv_axi4_ib_int_async (aw_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .aw_rpntr_gry_psram_slv_axi4_ib_int_async (aw_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_data_psram_slv_axi4_ib_int_async (ar_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_wpntr_gry_psram_slv_axi4_ib_int_async (ar_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_rpntr_bin_psram_slv_axi4_ib_int_async (ar_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .ar_rpntr_gry_psram_slv_axi4_ib_int_async (ar_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_data_psram_slv_axi4_ib_int_async (w_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_wpntr_gry_psram_slv_axi4_ib_int_async (w_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_rpntr_bin_psram_slv_axi4_ib_int_async (w_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .w_rpntr_gry_psram_slv_axi4_ib_int_async (w_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_data_psram_slv_axi4_ib_int_async (r_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_wpntr_gry_psram_slv_axi4_ib_int_async (r_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_rpntr_bin_psram_slv_axi4_ib_int_async (r_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .r_rpntr_gry_psram_slv_axi4_ib_int_async (r_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_data_psram_slv_axi4_ib_int_async (b_data_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_wpntr_gry_psram_slv_axi4_ib_int_async (b_wpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_rpntr_bin_psram_slv_axi4_ib_int_async (b_rpntr_bin_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .b_rpntr_gry_psram_slv_axi4_ib_int_async (b_rpntr_gry_psram_slv_axi4_ib_int_async),    // psram_slv_axi4_ib_int_async
  .paddr_pwm0_slv_apb4  (paddr_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pselx_pwm0_slv_apb4  (pselx_pwm0_slv_apb4),    // pwm0_slv_apb4
  .penable_pwm0_slv_apb4 (penable_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pwrite_pwm0_slv_apb4 (pwrite_pwm0_slv_apb4),    // pwm0_slv_apb4
  .prdata_pwm0_slv_apb4 (prdata_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pwdata_pwm0_slv_apb4 (pwdata_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pprot_pwm0_slv_apb4  (pprot_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pstrb_pwm0_slv_apb4  (pstrb_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pready_pwm0_slv_apb4 (pready_pwm0_slv_apb4),    // pwm0_slv_apb4
  .pslverr_pwm0_slv_apb4 (pslverr_pwm0_slv_apb4),    // pwm0_slv_apb4
  .paddr_pwm1_slv_apb4  (paddr_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pselx_pwm1_slv_apb4  (pselx_pwm1_slv_apb4),    // pwm1_slv_apb4
  .penable_pwm1_slv_apb4 (penable_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pwrite_pwm1_slv_apb4 (pwrite_pwm1_slv_apb4),    // pwm1_slv_apb4
  .prdata_pwm1_slv_apb4 (prdata_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pwdata_pwm1_slv_apb4 (pwdata_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pprot_pwm1_slv_apb4  (pprot_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pstrb_pwm1_slv_apb4  (pstrb_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pready_pwm1_slv_apb4 (pready_pwm1_slv_apb4),    // pwm1_slv_apb4
  .pslverr_pwm1_slv_apb4 (pslverr_pwm1_slv_apb4),    // pwm1_slv_apb4
  .paddr_pwm2_slv_apb4  (paddr_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pselx_pwm2_slv_apb4  (pselx_pwm2_slv_apb4),    // pwm2_slv_apb4
  .penable_pwm2_slv_apb4 (penable_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pwrite_pwm2_slv_apb4 (pwrite_pwm2_slv_apb4),    // pwm2_slv_apb4
  .prdata_pwm2_slv_apb4 (prdata_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pwdata_pwm2_slv_apb4 (pwdata_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pprot_pwm2_slv_apb4  (pprot_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pstrb_pwm2_slv_apb4  (pstrb_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pready_pwm2_slv_apb4 (pready_pwm2_slv_apb4),    // pwm2_slv_apb4
  .pslverr_pwm2_slv_apb4 (pslverr_pwm2_slv_apb4),    // pwm2_slv_apb4
  .paddr_qspi_slv_apb4  (paddr_qspi_slv_apb4),    // qspi_slv_apb4
  .pselx_qspi_slv_apb4  (pselx_qspi_slv_apb4),    // qspi_slv_apb4
  .penable_qspi_slv_apb4 (penable_qspi_slv_apb4),    // qspi_slv_apb4
  .pwrite_qspi_slv_apb4 (pwrite_qspi_slv_apb4),    // qspi_slv_apb4
  .prdata_qspi_slv_apb4 (prdata_qspi_slv_apb4),    // qspi_slv_apb4
  .pwdata_qspi_slv_apb4 (pwdata_qspi_slv_apb4),    // qspi_slv_apb4
  .pprot_qspi_slv_apb4  (pprot_qspi_slv_apb4),    // qspi_slv_apb4
  .pstrb_qspi_slv_apb4  (pstrb_qspi_slv_apb4),    // qspi_slv_apb4
  .pready_qspi_slv_apb4 (pready_qspi_slv_apb4),    // qspi_slv_apb4
  .pslverr_qspi_slv_apb4 (pslverr_qspi_slv_apb4),    // qspi_slv_apb4
  .paddr_rcu_slv_apb4   (paddr_rcu_slv_apb4),    // rcu_slv_apb4
  .pselx_rcu_slv_apb4   (pselx_rcu_slv_apb4),    // rcu_slv_apb4
  .penable_rcu_slv_apb4 (penable_rcu_slv_apb4),    // rcu_slv_apb4
  .pwrite_rcu_slv_apb4  (pwrite_rcu_slv_apb4),    // rcu_slv_apb4
  .prdata_rcu_slv_apb4  (prdata_rcu_slv_apb4),    // rcu_slv_apb4
  .pwdata_rcu_slv_apb4  (pwdata_rcu_slv_apb4),    // rcu_slv_apb4
  .pprot_rcu_slv_apb4   (pprot_rcu_slv_apb4),    // rcu_slv_apb4
  .pstrb_rcu_slv_apb4   (pstrb_rcu_slv_apb4),    // rcu_slv_apb4
  .pready_rcu_slv_apb4  (pready_rcu_slv_apb4),    // rcu_slv_apb4
  .pslverr_rcu_slv_apb4 (pslverr_rcu_slv_apb4),    // rcu_slv_apb4
  .paddr_rng_slv_apb4   (paddr_rng_slv_apb4),    // rng_slv_apb4
  .pselx_rng_slv_apb4   (pselx_rng_slv_apb4),    // rng_slv_apb4
  .penable_rng_slv_apb4 (penable_rng_slv_apb4),    // rng_slv_apb4
  .pwrite_rng_slv_apb4  (pwrite_rng_slv_apb4),    // rng_slv_apb4
  .prdata_rng_slv_apb4  (prdata_rng_slv_apb4),    // rng_slv_apb4
  .pwdata_rng_slv_apb4  (pwdata_rng_slv_apb4),    // rng_slv_apb4
  .pprot_rng_slv_apb4   (pprot_rng_slv_apb4),    // rng_slv_apb4
  .pstrb_rng_slv_apb4   (pstrb_rng_slv_apb4),    // rng_slv_apb4
  .pready_rng_slv_apb4  (pready_rng_slv_apb4),    // rng_slv_apb4
  .pslverr_rng_slv_apb4 (pslverr_rng_slv_apb4),    // rng_slv_apb4
  .paddr_rtc_slv_apb4   (paddr_rtc_slv_apb4),    // rtc_slv_apb4
  .pselx_rtc_slv_apb4   (pselx_rtc_slv_apb4),    // rtc_slv_apb4
  .penable_rtc_slv_apb4 (penable_rtc_slv_apb4),    // rtc_slv_apb4
  .pwrite_rtc_slv_apb4  (pwrite_rtc_slv_apb4),    // rtc_slv_apb4
  .prdata_rtc_slv_apb4  (prdata_rtc_slv_apb4),    // rtc_slv_apb4
  .pwdata_rtc_slv_apb4  (pwdata_rtc_slv_apb4),    // rtc_slv_apb4
  .pprot_rtc_slv_apb4   (pprot_rtc_slv_apb4),    // rtc_slv_apb4
  .pstrb_rtc_slv_apb4   (pstrb_rtc_slv_apb4),    // rtc_slv_apb4
  .pready_rtc_slv_apb4  (pready_rtc_slv_apb4),    // rtc_slv_apb4
  .pslverr_rtc_slv_apb4 (pslverr_rtc_slv_apb4),    // rtc_slv_apb4
  .awid_sdram_slv_axi4  (awid_sdram_slv_axi4),    // sdram_slv_axi4
  .awaddr_sdram_slv_axi4 (awaddr_sdram_slv_axi4),    // sdram_slv_axi4
  .awlen_sdram_slv_axi4 (awlen_sdram_slv_axi4),    // sdram_slv_axi4
  .awsize_sdram_slv_axi4 (awsize_sdram_slv_axi4),    // sdram_slv_axi4
  .awburst_sdram_slv_axi4 (awburst_sdram_slv_axi4),    // sdram_slv_axi4
  .awlock_sdram_slv_axi4 (awlock_sdram_slv_axi4),    // sdram_slv_axi4
  .awcache_sdram_slv_axi4 (awcache_sdram_slv_axi4),    // sdram_slv_axi4
  .awprot_sdram_slv_axi4 (awprot_sdram_slv_axi4),    // sdram_slv_axi4
  .awvalid_sdram_slv_axi4 (awvalid_sdram_slv_axi4),    // sdram_slv_axi4
  .awready_sdram_slv_axi4 (awready_sdram_slv_axi4),    // sdram_slv_axi4
  .wdata_sdram_slv_axi4 (wdata_sdram_slv_axi4),    // sdram_slv_axi4
  .wstrb_sdram_slv_axi4 (wstrb_sdram_slv_axi4),    // sdram_slv_axi4
  .wlast_sdram_slv_axi4 (wlast_sdram_slv_axi4),    // sdram_slv_axi4
  .wvalid_sdram_slv_axi4 (wvalid_sdram_slv_axi4),    // sdram_slv_axi4
  .wready_sdram_slv_axi4 (wready_sdram_slv_axi4),    // sdram_slv_axi4
  .bid_sdram_slv_axi4   (bid_sdram_slv_axi4),    // sdram_slv_axi4
  .bresp_sdram_slv_axi4 (bresp_sdram_slv_axi4),    // sdram_slv_axi4
  .bvalid_sdram_slv_axi4 (bvalid_sdram_slv_axi4),    // sdram_slv_axi4
  .bready_sdram_slv_axi4 (bready_sdram_slv_axi4),    // sdram_slv_axi4
  .arid_sdram_slv_axi4  (arid_sdram_slv_axi4),    // sdram_slv_axi4
  .araddr_sdram_slv_axi4 (araddr_sdram_slv_axi4),    // sdram_slv_axi4
  .arlen_sdram_slv_axi4 (arlen_sdram_slv_axi4),    // sdram_slv_axi4
  .arsize_sdram_slv_axi4 (arsize_sdram_slv_axi4),    // sdram_slv_axi4
  .arburst_sdram_slv_axi4 (arburst_sdram_slv_axi4),    // sdram_slv_axi4
  .arlock_sdram_slv_axi4 (arlock_sdram_slv_axi4),    // sdram_slv_axi4
  .arcache_sdram_slv_axi4 (arcache_sdram_slv_axi4),    // sdram_slv_axi4
  .arprot_sdram_slv_axi4 (arprot_sdram_slv_axi4),    // sdram_slv_axi4
  .arvalid_sdram_slv_axi4 (arvalid_sdram_slv_axi4),    // sdram_slv_axi4
  .arready_sdram_slv_axi4 (arready_sdram_slv_axi4),    // sdram_slv_axi4
  .rid_sdram_slv_axi4   (rid_sdram_slv_axi4),    // sdram_slv_axi4
  .rdata_sdram_slv_axi4 (rdata_sdram_slv_axi4),    // sdram_slv_axi4
  .rresp_sdram_slv_axi4 (rresp_sdram_slv_axi4),    // sdram_slv_axi4
  .rlast_sdram_slv_axi4 (rlast_sdram_slv_axi4),    // sdram_slv_axi4
  .rvalid_sdram_slv_axi4 (rvalid_sdram_slv_axi4),    // sdram_slv_axi4
  .rready_sdram_slv_axi4 (rready_sdram_slv_axi4),    // sdram_slv_axi4
  .aw_data_sdram_slv_axi4_ib_int_async (aw_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .aw_wpntr_gry_sdram_slv_axi4_ib_int_async (aw_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .aw_rpntr_bin_sdram_slv_axi4_ib_int_async (aw_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .aw_rpntr_gry_sdram_slv_axi4_ib_int_async (aw_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_data_sdram_slv_axi4_ib_int_async (ar_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_wpntr_gry_sdram_slv_axi4_ib_int_async (ar_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_rpntr_bin_sdram_slv_axi4_ib_int_async (ar_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .ar_rpntr_gry_sdram_slv_axi4_ib_int_async (ar_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_data_sdram_slv_axi4_ib_int_async (w_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_wpntr_gry_sdram_slv_axi4_ib_int_async (w_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_rpntr_bin_sdram_slv_axi4_ib_int_async (w_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .w_rpntr_gry_sdram_slv_axi4_ib_int_async (w_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_data_sdram_slv_axi4_ib_int_async (r_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_wpntr_gry_sdram_slv_axi4_ib_int_async (r_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_rpntr_bin_sdram_slv_axi4_ib_int_async (r_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .r_rpntr_gry_sdram_slv_axi4_ib_int_async (r_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_data_sdram_slv_axi4_ib_int_async (b_data_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_wpntr_gry_sdram_slv_axi4_ib_int_async (b_wpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_rpntr_bin_sdram_slv_axi4_ib_int_async (b_rpntr_bin_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .b_rpntr_gry_sdram_slv_axi4_ib_int_async (b_rpntr_gry_sdram_slv_axi4_ib_int_async),    // sdram_slv_axi4_ib_int_async
  .paddr_spi0_slv_apb4  (paddr_spi0_slv_apb4),    // spi0_slv_apb4
  .pselx_spi0_slv_apb4  (pselx_spi0_slv_apb4),    // spi0_slv_apb4
  .penable_spi0_slv_apb4 (penable_spi0_slv_apb4),    // spi0_slv_apb4
  .pwrite_spi0_slv_apb4 (pwrite_spi0_slv_apb4),    // spi0_slv_apb4
  .prdata_spi0_slv_apb4 (prdata_spi0_slv_apb4),    // spi0_slv_apb4
  .pwdata_spi0_slv_apb4 (pwdata_spi0_slv_apb4),    // spi0_slv_apb4
  .pprot_spi0_slv_apb4  (pprot_spi0_slv_apb4),    // spi0_slv_apb4
  .pstrb_spi0_slv_apb4  (pstrb_spi0_slv_apb4),    // spi0_slv_apb4
  .pready_spi0_slv_apb4 (pready_spi0_slv_apb4),    // spi0_slv_apb4
  .pslverr_spi0_slv_apb4 (pslverr_spi0_slv_apb4),    // spi0_slv_apb4
  .paddr_spi1_slv_apb4  (paddr_spi1_slv_apb4),    // spi1_slv_apb4
  .pselx_spi1_slv_apb4  (pselx_spi1_slv_apb4),    // spi1_slv_apb4
  .penable_spi1_slv_apb4 (penable_spi1_slv_apb4),    // spi1_slv_apb4
  .pwrite_spi1_slv_apb4 (pwrite_spi1_slv_apb4),    // spi1_slv_apb4
  .prdata_spi1_slv_apb4 (prdata_spi1_slv_apb4),    // spi1_slv_apb4
  .pwdata_spi1_slv_apb4 (pwdata_spi1_slv_apb4),    // spi1_slv_apb4
  .pprot_spi1_slv_apb4  (pprot_spi1_slv_apb4),    // spi1_slv_apb4
  .pstrb_spi1_slv_apb4  (pstrb_spi1_slv_apb4),    // spi1_slv_apb4
  .pready_spi1_slv_apb4 (pready_spi1_slv_apb4),    // spi1_slv_apb4
  .pslverr_spi1_slv_apb4 (pslverr_spi1_slv_apb4),    // spi1_slv_apb4
  .a_data_sys_gp_apb4_ib_int_async (a_data_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_wpntr_gry_sys_gp_apb4_ib_int_async (a_wpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_rpntr_bin_sys_gp_apb4_ib_int_async (a_rpntr_bin_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .a_rpntr_gry_sys_gp_apb4_ib_int_async (a_rpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_data_sys_gp_apb4_ib_int_async (w_data_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_wpntr_gry_sys_gp_apb4_ib_int_async (w_wpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_rpntr_bin_sys_gp_apb4_ib_int_async (w_rpntr_bin_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .w_rpntr_gry_sys_gp_apb4_ib_int_async (w_rpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_data_sys_gp_apb4_ib_int_async (d_data_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_wpntr_gry_sys_gp_apb4_ib_int_async (d_wpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_rpntr_bin_sys_gp_apb4_ib_int_async (d_rpntr_bin_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .d_rpntr_gry_sys_gp_apb4_ib_int_async (d_rpntr_gry_sys_gp_apb4_ib_int_async),    // sys_gp_apb4_ib_int_async
  .paddr_tim0_slv_apb4  (paddr_tim0_slv_apb4),    // tim0_slv_apb4
  .pselx_tim0_slv_apb4  (pselx_tim0_slv_apb4),    // tim0_slv_apb4
  .penable_tim0_slv_apb4 (penable_tim0_slv_apb4),    // tim0_slv_apb4
  .pwrite_tim0_slv_apb4 (pwrite_tim0_slv_apb4),    // tim0_slv_apb4
  .prdata_tim0_slv_apb4 (prdata_tim0_slv_apb4),    // tim0_slv_apb4
  .pwdata_tim0_slv_apb4 (pwdata_tim0_slv_apb4),    // tim0_slv_apb4
  .pprot_tim0_slv_apb4  (pprot_tim0_slv_apb4),    // tim0_slv_apb4
  .pstrb_tim0_slv_apb4  (pstrb_tim0_slv_apb4),    // tim0_slv_apb4
  .pready_tim0_slv_apb4 (pready_tim0_slv_apb4),    // tim0_slv_apb4
  .pslverr_tim0_slv_apb4 (pslverr_tim0_slv_apb4),    // tim0_slv_apb4
  .paddr_tim1_slv_apb4  (paddr_tim1_slv_apb4),    // tim1_slv_apb4
  .pselx_tim1_slv_apb4  (pselx_tim1_slv_apb4),    // tim1_slv_apb4
  .penable_tim1_slv_apb4 (penable_tim1_slv_apb4),    // tim1_slv_apb4
  .pwrite_tim1_slv_apb4 (pwrite_tim1_slv_apb4),    // tim1_slv_apb4
  .prdata_tim1_slv_apb4 (prdata_tim1_slv_apb4),    // tim1_slv_apb4
  .pwdata_tim1_slv_apb4 (pwdata_tim1_slv_apb4),    // tim1_slv_apb4
  .pprot_tim1_slv_apb4  (pprot_tim1_slv_apb4),    // tim1_slv_apb4
  .pstrb_tim1_slv_apb4  (pstrb_tim1_slv_apb4),    // tim1_slv_apb4
  .pready_tim1_slv_apb4 (pready_tim1_slv_apb4),    // tim1_slv_apb4
  .pslverr_tim1_slv_apb4 (pslverr_tim1_slv_apb4),    // tim1_slv_apb4
  .paddr_tim2_slv_apb4  (paddr_tim2_slv_apb4),    // tim2_slv_apb4
  .pselx_tim2_slv_apb4  (pselx_tim2_slv_apb4),    // tim2_slv_apb4
  .penable_tim2_slv_apb4 (penable_tim2_slv_apb4),    // tim2_slv_apb4
  .pwrite_tim2_slv_apb4 (pwrite_tim2_slv_apb4),    // tim2_slv_apb4
  .prdata_tim2_slv_apb4 (prdata_tim2_slv_apb4),    // tim2_slv_apb4
  .pwdata_tim2_slv_apb4 (pwdata_tim2_slv_apb4),    // tim2_slv_apb4
  .pprot_tim2_slv_apb4  (pprot_tim2_slv_apb4),    // tim2_slv_apb4
  .pstrb_tim2_slv_apb4  (pstrb_tim2_slv_apb4),    // tim2_slv_apb4
  .pready_tim2_slv_apb4 (pready_tim2_slv_apb4),    // tim2_slv_apb4
  .pslverr_tim2_slv_apb4 (pslverr_tim2_slv_apb4),    // tim2_slv_apb4
  .paddr_tim3_slv_apb4  (paddr_tim3_slv_apb4),    // tim3_slv_apb4
  .pselx_tim3_slv_apb4  (pselx_tim3_slv_apb4),    // tim3_slv_apb4
  .penable_tim3_slv_apb4 (penable_tim3_slv_apb4),    // tim3_slv_apb4
  .pwrite_tim3_slv_apb4 (pwrite_tim3_slv_apb4),    // tim3_slv_apb4
  .prdata_tim3_slv_apb4 (prdata_tim3_slv_apb4),    // tim3_slv_apb4
  .pwdata_tim3_slv_apb4 (pwdata_tim3_slv_apb4),    // tim3_slv_apb4
  .pprot_tim3_slv_apb4  (pprot_tim3_slv_apb4),    // tim3_slv_apb4
  .pstrb_tim3_slv_apb4  (pstrb_tim3_slv_apb4),    // tim3_slv_apb4
  .pready_tim3_slv_apb4 (pready_tim3_slv_apb4),    // tim3_slv_apb4
  .pslverr_tim3_slv_apb4 (pslverr_tim3_slv_apb4),    // tim3_slv_apb4
  .paddr_uart_slv_apb4  (paddr_uart_slv_apb4),    // uart_slv_apb4
  .pselx_uart_slv_apb4  (pselx_uart_slv_apb4),    // uart_slv_apb4
  .penable_uart_slv_apb4 (penable_uart_slv_apb4),    // uart_slv_apb4
  .pwrite_uart_slv_apb4 (pwrite_uart_slv_apb4),    // uart_slv_apb4
  .prdata_uart_slv_apb4 (prdata_uart_slv_apb4),    // uart_slv_apb4
  .pwdata_uart_slv_apb4 (pwdata_uart_slv_apb4),    // uart_slv_apb4
  .pprot_uart_slv_apb4  (pprot_uart_slv_apb4),    // uart_slv_apb4
  .pstrb_uart_slv_apb4  (pstrb_uart_slv_apb4),    // uart_slv_apb4
  .pready_uart_slv_apb4 (pready_uart_slv_apb4),    // uart_slv_apb4
  .pslverr_uart_slv_apb4 (pslverr_uart_slv_apb4),    // uart_slv_apb4
  .awid_vgalcd_mst_axi4 (awid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awaddr_vgalcd_mst_axi4 (awaddr_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awlen_vgalcd_mst_axi4 (awlen_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awsize_vgalcd_mst_axi4 (awsize_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awburst_vgalcd_mst_axi4 (awburst_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awlock_vgalcd_mst_axi4 (awlock_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awcache_vgalcd_mst_axi4 (awcache_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awprot_vgalcd_mst_axi4 (awprot_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awvalid_vgalcd_mst_axi4 (awvalid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .awready_vgalcd_mst_axi4 (awready_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .wdata_vgalcd_mst_axi4 (wdata_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .wstrb_vgalcd_mst_axi4 (wstrb_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .wlast_vgalcd_mst_axi4 (wlast_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .wvalid_vgalcd_mst_axi4 (wvalid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .wready_vgalcd_mst_axi4 (wready_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .bid_vgalcd_mst_axi4  (bid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .bresp_vgalcd_mst_axi4 (bresp_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .bvalid_vgalcd_mst_axi4 (bvalid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .bready_vgalcd_mst_axi4 (bready_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arid_vgalcd_mst_axi4 (arid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .araddr_vgalcd_mst_axi4 (araddr_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arlen_vgalcd_mst_axi4 (arlen_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arsize_vgalcd_mst_axi4 (arsize_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arburst_vgalcd_mst_axi4 (arburst_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arlock_vgalcd_mst_axi4 (arlock_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arcache_vgalcd_mst_axi4 (arcache_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arprot_vgalcd_mst_axi4 (arprot_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arvalid_vgalcd_mst_axi4 (arvalid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .arready_vgalcd_mst_axi4 (arready_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .rid_vgalcd_mst_axi4  (rid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .rdata_vgalcd_mst_axi4 (rdata_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .rresp_vgalcd_mst_axi4 (rresp_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .rlast_vgalcd_mst_axi4 (rlast_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .rvalid_vgalcd_mst_axi4 (rvalid_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .rready_vgalcd_mst_axi4 (rready_vgalcd_mst_axi4),    // vgalcd_mst_axi4
  .aw_data_vgalcd_mst_axi4_ib_int_async (aw_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async (aw_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async (aw_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async (aw_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_data_vgalcd_mst_axi4_ib_int_async (ar_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async (ar_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async (ar_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async (ar_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_data_vgalcd_mst_axi4_ib_int_async (w_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_wpntr_gry_vgalcd_mst_axi4_ib_int_async (w_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_rpntr_bin_vgalcd_mst_axi4_ib_int_async (w_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .w_rpntr_gry_vgalcd_mst_axi4_ib_int_async (w_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_data_vgalcd_mst_axi4_ib_int_async (r_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_wpntr_gry_vgalcd_mst_axi4_ib_int_async (r_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_rpntr_bin_vgalcd_mst_axi4_ib_int_async (r_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .r_rpntr_gry_vgalcd_mst_axi4_ib_int_async (r_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_data_vgalcd_mst_axi4_ib_int_async (b_data_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_wpntr_gry_vgalcd_mst_axi4_ib_int_async (b_wpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_rpntr_bin_vgalcd_mst_axi4_ib_int_async (b_rpntr_bin_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .b_rpntr_gry_vgalcd_mst_axi4_ib_int_async (b_rpntr_gry_vgalcd_mst_axi4_ib_int_async),    // vgalcd_mst_axi4_ib_int_async
  .paddr_vgalcd_slv_apb4 (paddr_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pselx_vgalcd_slv_apb4 (pselx_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .penable_vgalcd_slv_apb4 (penable_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pwrite_vgalcd_slv_apb4 (pwrite_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .prdata_vgalcd_slv_apb4 (prdata_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pwdata_vgalcd_slv_apb4 (pwdata_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pprot_vgalcd_slv_apb4 (pprot_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pstrb_vgalcd_slv_apb4 (pstrb_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pready_vgalcd_slv_apb4 (pready_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .pslverr_vgalcd_slv_apb4 (pslverr_vgalcd_slv_apb4),    // vgalcd_slv_apb4
  .clk_peri_100mclk     (clk_peri_100mclk),    // wdg_slv_apb4
  .clk_peri_100mresetn  (clk_peri_100mresetn),    // wdg_slv_apb4
  .paddr_wdg_slv_apb4   (paddr_wdg_slv_apb4),    // wdg_slv_apb4
  .pselx_wdg_slv_apb4   (pselx_wdg_slv_apb4),    // wdg_slv_apb4
  .penable_wdg_slv_apb4 (penable_wdg_slv_apb4),    // wdg_slv_apb4
  .pwrite_wdg_slv_apb4  (pwrite_wdg_slv_apb4),    // wdg_slv_apb4
  .prdata_wdg_slv_apb4  (prdata_wdg_slv_apb4),    // wdg_slv_apb4
  .pwdata_wdg_slv_apb4  (pwdata_wdg_slv_apb4),    // wdg_slv_apb4
  .pprot_wdg_slv_apb4   (pprot_wdg_slv_apb4),    // wdg_slv_apb4
  .pstrb_wdg_slv_apb4   (pstrb_wdg_slv_apb4),    // wdg_slv_apb4
  .pready_wdg_slv_apb4  (pready_wdg_slv_apb4),    // wdg_slv_apb4
  .pslverr_wdg_slv_apb4 (pslverr_wdg_slv_apb4),    // wdg_slv_apb4
  .clk_peri_100mclken   (clk_peri_100mclken)    // wdg_slv_apb4
);


nic400_cd_clk_peri_25m_ysyx_rv32     u_cd_clk_peri_25m (
  .awid_chiplink_slv_axi4_tpv (awid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awaddr_chiplink_slv_axi4_tpv (awaddr_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awlen_chiplink_slv_axi4_tpv (awlen_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awsize_chiplink_slv_axi4_tpv (awsize_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awburst_chiplink_slv_axi4_tpv (awburst_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awlock_chiplink_slv_axi4_tpv (awlock_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awcache_chiplink_slv_axi4_tpv (awcache_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awprot_chiplink_slv_axi4_tpv (awprot_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awvalid_chiplink_slv_axi4_tpv (awvalid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .awready_chiplink_slv_axi4_tpv (awready_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .wdata_chiplink_slv_axi4_tpv (wdata_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .wstrb_chiplink_slv_axi4_tpv (wstrb_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .wlast_chiplink_slv_axi4_tpv (wlast_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .wvalid_chiplink_slv_axi4_tpv (wvalid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .wready_chiplink_slv_axi4_tpv (wready_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .bid_chiplink_slv_axi4_tpv (bid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .bresp_chiplink_slv_axi4_tpv (bresp_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .bvalid_chiplink_slv_axi4_tpv (bvalid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .bready_chiplink_slv_axi4_tpv (bready_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arid_chiplink_slv_axi4_tpv (arid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .araddr_chiplink_slv_axi4_tpv (araddr_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arlen_chiplink_slv_axi4_tpv (arlen_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arsize_chiplink_slv_axi4_tpv (arsize_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arburst_chiplink_slv_axi4_tpv (arburst_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arlock_chiplink_slv_axi4_tpv (arlock_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arcache_chiplink_slv_axi4_tpv (arcache_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arprot_chiplink_slv_axi4_tpv (arprot_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arvalid_chiplink_slv_axi4_tpv (arvalid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .arready_chiplink_slv_axi4_tpv (arready_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .rid_chiplink_slv_axi4_tpv (rid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .rdata_chiplink_slv_axi4_tpv (rdata_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .rresp_chiplink_slv_axi4_tpv (rresp_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .rlast_chiplink_slv_axi4_tpv (rlast_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .rvalid_chiplink_slv_axi4_tpv (rvalid_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .rready_chiplink_slv_axi4_tpv (rready_chiplink_slv_axi4_tpv),    // chiplink_slv_axi4_tpv
  .aw_data_chiplink_slv_axi4_tpv_ib_int_async (aw_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (aw_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (aw_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (aw_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_data_chiplink_slv_axi4_tpv_ib_int_async (ar_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (ar_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (ar_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (ar_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_data_chiplink_slv_axi4_tpv_ib_int_async (w_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (w_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (w_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (w_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_data_chiplink_slv_axi4_tpv_ib_int_async (r_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (r_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (r_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (r_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_data_chiplink_slv_axi4_tpv_ib_int_async (b_data_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (b_wpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async (b_rpntr_bin_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async (b_rpntr_gry_chiplink_slv_axi4_tpv_ib_int_async),    // chiplink_slv_axi4_tpv_ib_int_async
  .aw_data_dma_axi4_cpu_ib_int_async (aw_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .aw_wpntr_gry_dma_axi4_cpu_ib_int_async (aw_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .aw_rpntr_bin_dma_axi4_cpu_ib_int_async (aw_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .aw_rpntr_gry_dma_axi4_cpu_ib_int_async (aw_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_data_dma_axi4_cpu_ib_int_async (ar_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_wpntr_gry_dma_axi4_cpu_ib_int_async (ar_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_rpntr_bin_dma_axi4_cpu_ib_int_async (ar_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .ar_rpntr_gry_dma_axi4_cpu_ib_int_async (ar_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_data_dma_axi4_cpu_ib_int_async (w_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_wpntr_gry_dma_axi4_cpu_ib_int_async (w_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_rpntr_bin_dma_axi4_cpu_ib_int_async (w_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .w_rpntr_gry_dma_axi4_cpu_ib_int_async (w_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_data_dma_axi4_cpu_ib_int_async (r_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_wpntr_gry_dma_axi4_cpu_ib_int_async (r_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_rpntr_bin_dma_axi4_cpu_ib_int_async (r_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .r_rpntr_gry_dma_axi4_cpu_ib_int_async (r_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_data_dma_axi4_cpu_ib_int_async (b_data_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_wpntr_gry_dma_axi4_cpu_ib_int_async (b_wpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_rpntr_bin_dma_axi4_cpu_ib_int_async (b_rpntr_bin_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .b_rpntr_gry_dma_axi4_cpu_ib_int_async (b_rpntr_gry_dma_axi4_cpu_ib_int_async),    // dma_axi4_cpu_ib_int_async
  .awid_dma_axi4_cpu_s  (awid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awaddr_dma_axi4_cpu_s (awaddr_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awlen_dma_axi4_cpu_s (awlen_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awsize_dma_axi4_cpu_s (awsize_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awburst_dma_axi4_cpu_s (awburst_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awlock_dma_axi4_cpu_s (awlock_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awcache_dma_axi4_cpu_s (awcache_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awprot_dma_axi4_cpu_s (awprot_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awvalid_dma_axi4_cpu_s (awvalid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .awready_dma_axi4_cpu_s (awready_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .wdata_dma_axi4_cpu_s (wdata_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .wstrb_dma_axi4_cpu_s (wstrb_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .wlast_dma_axi4_cpu_s (wlast_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .wvalid_dma_axi4_cpu_s (wvalid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .wready_dma_axi4_cpu_s (wready_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .bid_dma_axi4_cpu_s   (bid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .bresp_dma_axi4_cpu_s (bresp_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .bvalid_dma_axi4_cpu_s (bvalid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .bready_dma_axi4_cpu_s (bready_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arid_dma_axi4_cpu_s  (arid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .araddr_dma_axi4_cpu_s (araddr_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arlen_dma_axi4_cpu_s (arlen_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arsize_dma_axi4_cpu_s (arsize_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arburst_dma_axi4_cpu_s (arburst_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arlock_dma_axi4_cpu_s (arlock_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arcache_dma_axi4_cpu_s (arcache_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arprot_dma_axi4_cpu_s (arprot_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arvalid_dma_axi4_cpu_s (arvalid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .arready_dma_axi4_cpu_s (arready_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .rid_dma_axi4_cpu_s   (rid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .rdata_dma_axi4_cpu_s (rdata_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .rresp_dma_axi4_cpu_s (rresp_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .rlast_dma_axi4_cpu_s (rlast_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .rvalid_dma_axi4_cpu_s (rvalid_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .rready_dma_axi4_cpu_s (rready_dma_axi4_cpu_s),    // dma_axi4_cpu_s
  .pack_i2s_slv_apb4_int_slave_async (pack_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_slave_async
  .preq_i2s_slv_apb4_int_slave_async (preq_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_slave_async
  .pfwdpayld_i2s_slv_apb4_int_slave_async (pfwdpayld_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_slave_async
  .prevpayld_i2s_slv_apb4_int_slave_async (prevpayld_tpv_gp_apb4_i2s_slv_apb4_int_async),    // i2s_slv_apb4_int_slave_async
  .paddr_spfs_slv_apb4_tpv (paddr_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pselx_spfs_slv_apb4_tpv (pselx_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .penable_spfs_slv_apb4_tpv (penable_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pwrite_spfs_slv_apb4_tpv (pwrite_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .prdata_spfs_slv_apb4_tpv (prdata_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pwdata_spfs_slv_apb4_tpv (pwdata_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pprot_spfs_slv_apb4_tpv (pprot_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pstrb_spfs_slv_apb4_tpv (pstrb_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pready_spfs_slv_apb4_tpv (pready_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .pslverr_spfs_slv_apb4_tpv (pslverr_spfs_slv_apb4_tpv),    // spfs_slv_apb4_tpv
  .a_data_tpv_gp_apb4_ib_int_async (a_data_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .a_wpntr_gry_tpv_gp_apb4_ib_int_async (a_wpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .a_rpntr_bin_tpv_gp_apb4_ib_int_async (a_rpntr_bin_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .a_rpntr_gry_tpv_gp_apb4_ib_int_async (a_rpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_data_tpv_gp_apb4_ib_int_async (w_data_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_wpntr_gry_tpv_gp_apb4_ib_int_async (w_wpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_rpntr_bin_tpv_gp_apb4_ib_int_async (w_rpntr_bin_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .w_rpntr_gry_tpv_gp_apb4_ib_int_async (w_rpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_data_tpv_gp_apb4_ib_int_async (d_data_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_wpntr_gry_tpv_gp_apb4_ib_int_async (d_wpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_rpntr_bin_tpv_gp_apb4_ib_int_async (d_rpntr_bin_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .d_rpntr_gry_tpv_gp_apb4_ib_int_async (d_rpntr_gry_tpv_gp_apb4_ib_int_async),    // tpv_gp_apb4_ib_int_async
  .clk_peri_25mclk      (clk_peri_25mclk),    // uart_slv_apb4_tpv
  .clk_peri_25mresetn   (clk_peri_25mresetn),    // uart_slv_apb4_tpv
  .paddr_uart_slv_apb4_tpv (paddr_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pselx_uart_slv_apb4_tpv (pselx_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .penable_uart_slv_apb4_tpv (penable_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pwrite_uart_slv_apb4_tpv (pwrite_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .prdata_uart_slv_apb4_tpv (prdata_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pwdata_uart_slv_apb4_tpv (pwdata_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pprot_uart_slv_apb4_tpv (pprot_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pstrb_uart_slv_apb4_tpv (pstrb_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pready_uart_slv_apb4_tpv (pready_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .pslverr_uart_slv_apb4_tpv (pslverr_uart_slv_apb4_tpv),    // uart_slv_apb4_tpv
  .clk_peri_25mclken    (clk_peri_25mclken)    // uart_slv_apb4_tpv
);



endmodule
